| [4] | 1 | /* Definitions of several known BIOS addresses. The addresses listed here
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| 2 | * are found in three memory areas that have been defined in <ibm/memory.h>.
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| 3 | * - the BIOS interrupt vectors
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| 4 | * - the BIOS data area
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| 5 | * - the motherboard BIOS memory
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| 6 | *
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| 7 | * Created: March 2005, Jorrit N. Herder
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| 8 | */
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| 9 |
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| 10 | #ifndef _BIOS_H
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| 11 | #define _BIOS_H
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| 12 |
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| 13 | /* PART I --
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| 14 | * The BIOS interrupt vector table (IVT) area (1024 B as of address 0x0000).
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| 15 | * Although this area holds 256 interrupt vectors (with jump addresses), some
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| 16 | * vectors actually contain important BIOS data. Some addresses are below.
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| 17 | */
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| 18 | #define BIOS_EQUIP_CHECK_ADDR 0x0044
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| 19 | #define BIOS_EQUIP_CHECK_SIZE 4L
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| 20 |
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| 21 | #define BIOS_VIDEO_PARAMS_ADDR 0x0074
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| 22 | #define BIOS_VIDEO_PARAMS_SIZE 4L
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| 23 |
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| 24 | #define BIOS_FLOP_PARAMS_ADDR 0x0078
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| 25 | #define BIOS_FLOP_PARAMS_SIZE 4L
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| 26 |
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| 27 | #define BIOS_HD0_PARAMS_ADDR 0x0104 /* disk 0 parameters */
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| 28 | #define BIOS_HD0_PARAMS_SIZE 4L
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| 29 |
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| 30 | #define BIOS_HD1_PARAMS_ADDR 0x0118 /* disk 1 parameters */
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| 31 | #define BIOS_HD1_PARAMS_SIZE 4L
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| 32 |
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| 33 | /* PART I --
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| 34 | * Addresses in the BIOS data area (256 B as of address 0x0400). The addresses
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| 35 | * listed below are the most important ones, and the ones that are currently
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| 36 | * used. Other addresses may be defined below when new features are added.
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| 37 | */
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| 38 |
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| 39 | /* Serial ports (COM1-COM4). */
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| 40 | #define COM1_IO_PORT_ADDR 0x400 /* COM1 port address */
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| 41 | #define COM1_IO_PORT_SIZE 2L
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| 42 | #define COM2_IO_PORT_ADDR 0x402 /* COM2 port address */
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| 43 | #define COM2_IO_PORT_SIZE 2L
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| 44 | #define COM3_IO_PORT_ADDR 0x404 /* COM3 port address */
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| 45 | #define COM3_IO_PORT_SIZE 2L
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| 46 | #define COM4_IO_PORT_ADDR 0x406 /* COM4 port address */
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| 47 | #define COM4_IO_PORT_SIZE 2L
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| 48 |
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| 49 | /* Parallel ports (LPT1-LPT4). */
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| 50 | #define LPT1_IO_PORT_ADDR 0x408 /* LPT1 port address */
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| 51 | #define LPT1_IO_PORT_SIZE 2L
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| 52 | #define LPT2_IO_PORT_ADDR 0x40A /* LPT2 port address */
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| 53 | #define LPT2_IO_PORT_SIZE 2L
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| 54 | #define LPT3_IO_PORT_ADDR 0x40C /* LPT3 port address */
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| 55 | #define LPT3_IO_PORT_SIZE 2L
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| 56 | #define LPT4_IO_PORT_ADDR 0x40E /* LPT4 port (except on PS/2) */
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| 57 | #define LPT4_IO_PORT_SIZE 2L
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| 58 |
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| 59 | /* Video controller (VDU). */
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| 60 | #define VDU_SCREEN_COLS_ADDR 0x44A /* VDU nr of screen columns */
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| 61 | #define VDU_SCREEN_COLS_SIZE 2L
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| 62 |
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| 63 | /* Base I/O port address for active 6845 CRT controller. */
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| 64 | #define VDU_CRT_BASE_ADDR 0x463 /* 3B4h = mono, 3D4h = color */
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| 65 | #define VDU_CRT_BASE_SIZE 2L
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| 66 |
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| 67 | /* Soft reset flags to control shutdown. */
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| 68 | #define SOFT_RESET_FLAG_ADDR 0x472 /* soft reset flag on Ctl-Alt-Del */
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| 69 | #define SOFT_RESET_FLAG_SIZE 2L
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| 70 | #define STOP_MEM_CHECK 0x1234 /* bypass memory tests & CRT init */
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| 71 | #define PRESERVE_MEMORY 0x4321 /* preserve memory */
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| 72 | #define SYSTEM_SUSPEND 0x5678 /* system suspend */
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| 73 | #define MANUFACTURER_TEST 0x9ABC /* manufacturer test */
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| 74 | #define CONVERTIBLE_POST 0xABCD /* convertible POST loop */
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| 75 | /* ... many other values are used during POST */
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| 76 |
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| 77 | /* Hard disk parameters. (Also see BIOS interrupt vector table above.) */
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| 78 | #define NR_HD_DRIVES_ADDR 0x475 /* number of hard disk drives */
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| 79 | #define NR_HD_DRIVES_SIZE 1L
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| 80 |
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| 81 | /* Parallel ports (LPT1-LPT4) timeout values. */
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| 82 | #define LPT1_TIMEOUT_ADDR 0x478 /* time-out value for LPT1 */
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| 83 | #define LPT1_TIMEOUT_SIZE 1L
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| 84 | #define LPT2_TIMEOUT_ADDR 0x479 /* time-out value for LPT2 */
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| 85 | #define LPT2_TIMEOUT_SIZE 1L
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| 86 | #define LPT3_TIMEOUT_ADDR 0x47A /* time-out value for LPT3 */
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| 87 | #define LPT3_TIMEOUT_SIZE 1L
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| 88 | #define LPT4_TIMEOUT_ADDR 0x47B /* time-out for LPT4 (except PS/2) */
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| 89 | #define LPT4_TIMEOUT_SIZE 1L
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| 90 |
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| 91 | /* Serial ports (COM1-COM4) timeout values. */
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| 92 | #define COM1_TIMEOUT_ADDR 0x47C /* time-out value for COM1 */
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| 93 | #define COM1_TIMEOUT_SIZE 1L
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| 94 | #define COM2_TIMEOUT_ADDR 0x47D /* time-out value for COM2 */
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| 95 | #define COM2_TIMEOUT_SIZE 1L
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| 96 | #define COM3_TIMEOUT_ADDR 0x47E /* time-out value for COM3 */
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| 97 | #define COM3_TIMEOUT_SIZE 1L
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| 98 | #define COM4_TIMEOUT_ADDR 0x47F /* time-out value for COM4 */
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| 99 | #define COM4_TIMEOUT_SIZE 1L
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| 100 |
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| 101 | /* Video controller (VDU). */
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| 102 | #define VDU_SCREEN_ROWS_ADDR 0x484 /* screen rows (less 1, EGA+)*/
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| 103 | #define VDU_SCREEN_ROWS_SIZE 1L
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| 104 | #define VDU_FONTLINES_ADDR 0x485 /* point height of char matrix */
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| 105 | #define VDU_FONTLINES_SIZE 2L
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| 106 |
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| 107 | /* Video controller (VDU). */
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| 108 | #define VDU_VIDEO_MODE_ADDR 0x49A /* current video mode */
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| 109 | #define VDU_VIDEO_MODE_SIZE 1L
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| 110 |
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| 111 | /* PART III --
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| 112 | * The motherboard BIOS memory contains some known values that are currently
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| 113 | * in use. Other sections in the upper memory area (UMA) addresses vary in
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| 114 | * size and locus and are not further defined here. A rough map is given in
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| 115 | * <ibm/memory.h>.
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| 116 | */
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| 117 |
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| 118 | /* Machine ID (we're interested in PS/2 and AT models). */
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| 119 | #define MACHINE_ID_ADDR 0xFFFFE /* BIOS machine ID byte */
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| 120 | #define MACHINE_ID_SIZE 1L
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| 121 | #define PS_386_MACHINE 0xF8 /* ID byte for PS/2 modela 70/80 */
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| 122 | #define PC_AT_MACHINE 0xFC /* PC/AT, PC/XT286, PS/2 models 50/60 */
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| 123 |
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| 124 | #endif /* _BIOS_H */
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| 125 |
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