| [9] | 1 | /*
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| 2 | wdeth.h
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| 3 |
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| 4 | Created: before Dec 28, 1992 by Philip Homburg
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| 5 | */
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| 6 |
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| 7 | #ifndef WDETH_H
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| 8 | #define WDETH_H
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| 9 |
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| 10 | /* Western Digital Ethercard Plus, or WD8003E card. */
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| 11 |
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| 12 | #define EPL_REG0 0x0 /* Control(write) and status(read) */
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| 13 | #define EPL_REG1 0x1
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| 14 | #define EPL_REG2 0x2
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| 15 | #define EPL_REG3 0x3
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| 16 | #define EPL_REG4 0x4
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| 17 | #define EPL_REG5 0x5
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| 18 | #define EPL_REG6 0x6
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| 19 | #define EPL_REG7 0x7
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| 20 | #define EPL_EA0 0x8 /* Most significant eaddr byte */
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| 21 | #define EPL_EA1 0x9
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| 22 | #define EPL_EA2 0xA
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| 23 | #define EPL_EA3 0xB
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| 24 | #define EPL_EA4 0xC
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| 25 | #define EPL_EA5 0xD /* Least significant eaddr byte */
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| 26 | #define EPL_TLB 0xE
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| 27 | #define EPL_CHKSUM 0xF /* sum from epl_ea0 upto here is 0xFF */
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| 28 | #define EPL_DP8390 0x10 /* NatSemi chip */
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| 29 |
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| 30 | #define EPL_MSR EPL_REG0 /* memory select register */
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| 31 | #define EPL_ICR EPL_REG1 /* interface configuration register */
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| 32 | #define EPL_IRR EPL_REG4 /* interrupt request register (IRR) */
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| 33 | #define EPL_790_HWR EPL_REG4 /* '790 hardware support register */
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| 34 | #define EPL_LAAR EPL_REG5 /* LA address register (write only) */
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| 35 | #define EPL_790_ICR EPL_REG6 /* '790 interrupt control register */
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| 36 | #define EPL_GP2 EPL_REG7 /* general purpose register 2 */
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| 37 | #define EPL_790_B EPL_EA3 /* '790 memory register */
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| 38 | #define EPL_790_GCR EPL_EA5 /* '790 General Control Register */
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| 39 |
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| 40 | /* Bits in EPL_MSR */
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| 41 | #define E_MSR_MEMADDR 0x3F /* Bits SA18-SA13, SA19 implicit 1 */
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| 42 | #define E_MSR_MENABLE 0x40 /* Memory Enable */
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| 43 | #define E_MSR_RESET 0x80 /* Software Reset */
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| 44 |
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| 45 | /* Bits in EPL_ICR */
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| 46 | #define E_ICR_16BIT 0x01 /* 16 bit bus */
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| 47 | #define E_ICR_IR2 0x04 /* bit 2 of encoded IRQ */
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| 48 | #define E_ICR_MEMBIT 0x08 /* 583 mem size mask */
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| 49 |
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| 50 | /* Bits in EPL_IRR */
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| 51 | #define E_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
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| 52 | #define E_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
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| 53 | #define E_IRR_IEN 0x80 /* enable interrupts */
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| 54 |
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| 55 | /* Bits in EPL_LAAR */
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| 56 | #define E_LAAR_A19 0x01 /* address lines for above 1M ram */
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| 57 | #define E_LAAR_A20 0x02 /* address lines for above 1M ram */
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| 58 | #define E_LAAR_A21 0x04 /* address lines for above 1M ram */
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| 59 | #define E_LAAR_A22 0x08 /* address lines for above 1M ram */
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| 60 | #define E_LAAR_A23 0x10 /* address lines for above 1M ram */
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| 61 | #define E_LAAR_SOFTINT 0x20 /* enable software interrupt */
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| 62 | #define E_LAAR_LAN16E 0x40 /* enables 16 bit RAM for LAN */
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| 63 | #define E_LAAR_MEM16E 0x80 /* enables 16 bit RAM for host */
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| 64 |
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| 65 | /* Bits and values in EPL_TLB */
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| 66 | #define E_TLB_EB 0x05 /* WD8013EB */
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| 67 | #define E_TLB_E 0x27 /* WD8013 Elite */
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| 68 | #define E_TLB_SMCE 0x29 /* SMC Elite 16 */
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| 69 | #define E_TLB_SMC8216T 0x2A /* SMC 8216 T */
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| 70 | #define E_TLB_SMC8216C 0x2B /* SMC 8216 C */
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| 71 |
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| 72 | #define E_TLB_REV 0x1F /* revision mask */
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| 73 | #define E_TLB_SOFT 0x20 /* soft config */
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| 74 | #define E_TLB_RAM 0x40 /* extra ram bit */
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| 75 |
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| 76 | /* Bits in EPL_790_HWR */
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| 77 | #define E_790_HWR_SWH 0x80 /* switch register set */
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| 78 |
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| 79 | /* Bits in EPL_790_ICR */
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| 80 | #define E_790_ICR_EIL 0x01 /* enable interrupts */
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| 81 |
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| 82 | /* Bits in EPL_790_GCR when E_790_HWR_SWH is set in EPL_790_HWR */
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| 83 | #define E_790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
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| 84 | #define E_790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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| 85 | #define E_790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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| 86 |
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| 87 | #define inb_we(dep, reg) (inb(dep->de_base_port+reg))
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| 88 | #define outb_we(dep, reg, data) (outb(dep->de_base_port+reg, data))
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| 89 |
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| 90 | #endif /* WDETH_H */
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| 91 |
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| 92 | /*
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| 93 | * $PchId: wdeth.h,v 1.6 2003/09/10 19:29:52 philip Exp $
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| 94 | */
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