| 1 | /*
|
|---|
| 2 | wdeth.h
|
|---|
| 3 |
|
|---|
| 4 | Created: before Dec 28, 1992 by Philip Homburg
|
|---|
| 5 | */
|
|---|
| 6 |
|
|---|
| 7 | #ifndef WDETH_H
|
|---|
| 8 | #define WDETH_H
|
|---|
| 9 |
|
|---|
| 10 | /* Western Digital Ethercard Plus, or WD8003E card. */
|
|---|
| 11 |
|
|---|
| 12 | #define EPL_REG0 0x0 /* Control(write) and status(read) */
|
|---|
| 13 | #define EPL_REG1 0x1
|
|---|
| 14 | #define EPL_REG2 0x2
|
|---|
| 15 | #define EPL_REG3 0x3
|
|---|
| 16 | #define EPL_REG4 0x4
|
|---|
| 17 | #define EPL_REG5 0x5
|
|---|
| 18 | #define EPL_REG6 0x6
|
|---|
| 19 | #define EPL_REG7 0x7
|
|---|
| 20 | #define EPL_EA0 0x8 /* Most significant eaddr byte */
|
|---|
| 21 | #define EPL_EA1 0x9
|
|---|
| 22 | #define EPL_EA2 0xA
|
|---|
| 23 | #define EPL_EA3 0xB
|
|---|
| 24 | #define EPL_EA4 0xC
|
|---|
| 25 | #define EPL_EA5 0xD /* Least significant eaddr byte */
|
|---|
| 26 | #define EPL_TLB 0xE
|
|---|
| 27 | #define EPL_CHKSUM 0xF /* sum from epl_ea0 upto here is 0xFF */
|
|---|
| 28 | #define EPL_DP8390 0x10 /* NatSemi chip */
|
|---|
| 29 |
|
|---|
| 30 | #define EPL_MSR EPL_REG0 /* memory select register */
|
|---|
| 31 | #define EPL_ICR EPL_REG1 /* interface configuration register */
|
|---|
| 32 | #define EPL_IRR EPL_REG4 /* interrupt request register (IRR) */
|
|---|
| 33 | #define EPL_790_HWR EPL_REG4 /* '790 hardware support register */
|
|---|
| 34 | #define EPL_LAAR EPL_REG5 /* LA address register (write only) */
|
|---|
| 35 | #define EPL_790_ICR EPL_REG6 /* '790 interrupt control register */
|
|---|
| 36 | #define EPL_GP2 EPL_REG7 /* general purpose register 2 */
|
|---|
| 37 | #define EPL_790_B EPL_EA3 /* '790 memory register */
|
|---|
| 38 | #define EPL_790_GCR EPL_EA5 /* '790 General Control Register */
|
|---|
| 39 |
|
|---|
| 40 | /* Bits in EPL_MSR */
|
|---|
| 41 | #define E_MSR_MEMADDR 0x3F /* Bits SA18-SA13, SA19 implicit 1 */
|
|---|
| 42 | #define E_MSR_MENABLE 0x40 /* Memory Enable */
|
|---|
| 43 | #define E_MSR_RESET 0x80 /* Software Reset */
|
|---|
| 44 |
|
|---|
| 45 | /* Bits in EPL_ICR */
|
|---|
| 46 | #define E_ICR_16BIT 0x01 /* 16 bit bus */
|
|---|
| 47 | #define E_ICR_IR2 0x04 /* bit 2 of encoded IRQ */
|
|---|
| 48 | #define E_ICR_MEMBIT 0x08 /* 583 mem size mask */
|
|---|
| 49 |
|
|---|
| 50 | /* Bits in EPL_IRR */
|
|---|
| 51 | #define E_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
|
|---|
| 52 | #define E_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
|
|---|
| 53 | #define E_IRR_IEN 0x80 /* enable interrupts */
|
|---|
| 54 |
|
|---|
| 55 | /* Bits in EPL_LAAR */
|
|---|
| 56 | #define E_LAAR_A19 0x01 /* address lines for above 1M ram */
|
|---|
| 57 | #define E_LAAR_A20 0x02 /* address lines for above 1M ram */
|
|---|
| 58 | #define E_LAAR_A21 0x04 /* address lines for above 1M ram */
|
|---|
| 59 | #define E_LAAR_A22 0x08 /* address lines for above 1M ram */
|
|---|
| 60 | #define E_LAAR_A23 0x10 /* address lines for above 1M ram */
|
|---|
| 61 | #define E_LAAR_SOFTINT 0x20 /* enable software interrupt */
|
|---|
| 62 | #define E_LAAR_LAN16E 0x40 /* enables 16 bit RAM for LAN */
|
|---|
| 63 | #define E_LAAR_MEM16E 0x80 /* enables 16 bit RAM for host */
|
|---|
| 64 |
|
|---|
| 65 | /* Bits and values in EPL_TLB */
|
|---|
| 66 | #define E_TLB_EB 0x05 /* WD8013EB */
|
|---|
| 67 | #define E_TLB_E 0x27 /* WD8013 Elite */
|
|---|
| 68 | #define E_TLB_SMCE 0x29 /* SMC Elite 16 */
|
|---|
| 69 | #define E_TLB_SMC8216T 0x2A /* SMC 8216 T */
|
|---|
| 70 | #define E_TLB_SMC8216C 0x2B /* SMC 8216 C */
|
|---|
| 71 |
|
|---|
| 72 | #define E_TLB_REV 0x1F /* revision mask */
|
|---|
| 73 | #define E_TLB_SOFT 0x20 /* soft config */
|
|---|
| 74 | #define E_TLB_RAM 0x40 /* extra ram bit */
|
|---|
| 75 |
|
|---|
| 76 | /* Bits in EPL_790_HWR */
|
|---|
| 77 | #define E_790_HWR_SWH 0x80 /* switch register set */
|
|---|
| 78 |
|
|---|
| 79 | /* Bits in EPL_790_ICR */
|
|---|
| 80 | #define E_790_ICR_EIL 0x01 /* enable interrupts */
|
|---|
| 81 |
|
|---|
| 82 | /* Bits in EPL_790_GCR when E_790_HWR_SWH is set in EPL_790_HWR */
|
|---|
| 83 | #define E_790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
|
|---|
| 84 | #define E_790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
|
|---|
| 85 | #define E_790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
|
|---|
| 86 |
|
|---|
| 87 | #define inb_we(dep, reg) (inb(dep->de_base_port+reg))
|
|---|
| 88 | #define outb_we(dep, reg, data) (outb(dep->de_base_port+reg, data))
|
|---|
| 89 |
|
|---|
| 90 | #endif /* WDETH_H */
|
|---|
| 91 |
|
|---|
| 92 | /*
|
|---|
| 93 | * $PchId: wdeth.h,v 1.6 2003/09/10 19:29:52 philip Exp $
|
|---|
| 94 | */
|
|---|
