| [9] | 1 | /*
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| 2 | ** File: 3c501.h Jan. 14, 1997
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| 3 | **
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| 4 | ** Author: Giovanni Falzoni <gfalzoni@inwind.it>
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| 5 | **
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| 6 | ** Interface description for 3Com Etherlink boards
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| 7 | **
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| 8 | ** $Log: 3c501.h,v $
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| 9 | ** Revision 1.1 2005/06/29 10:16:46 beng
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| 10 | ** Import of dpeth 3c501/3c509b/.. ethernet driver by
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| 11 | ** Giovanni Falzoni <fgalzoni@inwind.it>.
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| 12 | **
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| 13 | ** Revision 2.0 2005/06/26 16:16:46 lsodgf0
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| 14 | ** Initial revision for Minix 3.0.6
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| 15 | **
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| 16 | ** $Id: 3c501.h,v 1.1 2005/06/29 10:16:46 beng Exp $
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| 17 | */
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| 18 |
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| 19 | /* The various board command registers */
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| 20 | #define EL1_ADDRESS 0x00 /* Board station address, 6 bytes */
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| 21 | #define EL1_RECV 0x06 /* Board Receive Config/Status Reg. */
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| 22 | #define EL1_XMIT 0x07 /* Board Transmit Config/Status Reg. */
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| 23 | #define EL1_XMITPTR 0x08 /* Transmit buffer pointer (word access) */
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| 24 | #define EL1_RECVPTR 0x0A /* Receive buffer pointer (word access) */
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| 25 | #define EL1_SAPROM 0x0C /* Window on Station Addr prom */
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| 26 | #define EL1_CSR 0x0E /* Board Command/Status Register */
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| 27 | #define EL1_DATAPORT 0x0F /* Window on packet buffer (Data Port) */
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| 28 |
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| 29 | /* Bits in EL1_RECV, interrupt enable on write, status when read */
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| 30 | #define ERSR_NONE 0x00 /* Match mode in bits 5-6 (wo) */
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| 31 | #define ERSR_ALL 0x40 /* Promiscuous receive (wo) */
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| 32 | #define ERSR_BROAD 0x80 /* Station address plus broadcast (wo) */
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| 33 | #define ERSR_MULTI 0x80 /* Station address plus multicast 0xC0 */
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| 34 | #define ERSR_STALE 0x80 /* Receive status previously read (ro) */
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| 35 | #define ERSR_GOOD 0x20 /* Well formed packets only (rw) */
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| 36 | #define ERSR_ANY 0x10 /* Any packet, even with errors (rw) */
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| 37 | #define ERSR_SHORT 0x08 /* Short frame (rw) */
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| 38 | #define ERSR_DRIBBLE 0x04 /* Dribble error (rw) */
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| 39 | #define ERSR_FCS 0x02 /* CRC error (rw) */
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| 40 | #define ERSR_OVER 0x01 /* Data overflow (rw) */
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| 41 |
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| 42 | #define ERSR_RERROR (ERSR_SHORT|ERSR_DRIBBLE|ERSR_FCS|ERSR_OVER)
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| 43 | #define ERSR_RMASK (ERSR_GOOD|ERSR_RERROR)/*(ERSR_GOOD|ERSR_ANY|ERSR_RERROR)*/
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| 44 |
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| 45 | /* Bits in EL1_XMIT, interrupt enable on write, status when read */
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| 46 | #define EXSR_IDLE 0x08 /* Transmit idle (send completed) */
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| 47 | #define EXSR_16JAM 0x04 /* Packet sending got 16 collisions */
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| 48 | #define EXSR_JAM 0x02 /* Packet sending got a collision */
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| 49 | #define EXSR_UNDER 0x01 /* Data underflow in sending */
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| 50 |
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| 51 | /* Bits in EL1_CSR (Configuration Status Register) */
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| 52 | #define ECSR_RESET 0x80 /* Reset the controller (wo) */
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| 53 | #define ECSR_XMTBSY 0x80 /* Transmitter busy (ro) */
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| 54 | #define ECSR_RIDE 0x01 /* Request interrupt/DMA enable (rw) */
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| 55 | #define ECSR_DMA 0x20 /* DMA request (rw) */
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| 56 | #define ECSR_EDMA 0x10 /* DMA done (ro) */
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| 57 | #define ECSR_CRC 0x02 /* Causes CRC error on transmit (wo) */
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| 58 | #define ECSR_RCVBSY 0x01 /* Receive in progress (ro) */
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| 59 | #define ECSR_LOOP (3<<2) /* 2 bit field in bits 2,3, loopback */
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| 60 | #define ECSR_RECV (2<<2) /* Gives buffer to receiver (rw) */
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| 61 | #define ECSR_XMIT (1<<2) /* Gives buffer to transmit (rw) */
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| 62 | #define ECSR_SYS (0<<2) /* Gives buffer to processor (wo) */
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| 63 |
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| 64 | #define EL1_BFRSIZ 2048 /* Number of bytes in board buffer */
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| 65 |
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| 66 | #define inb_el1(dep,reg) (inb(dep->de_base_port+(reg)))
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| 67 | #define inw_el1(dep,reg) (inw(dep->de_base_port+(reg)))
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| 68 | #define outb_el1(dep,reg,data) (outb(dep->de_base_port+(reg),data))
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| 69 | #define outw_el1(dep,reg,data) (outw(dep->de_base_port+(reg),data))
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| 70 |
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| 71 | /** 3c501.h **/
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