source: trunk/minix/drivers/dpeth/3c503.c@ 9

Last change on this file since 9 was 9, checked in by Mattia Monga, 13 years ago

Minix 3.1.2a
File size: 5.3 KB
RevLine 
[9]1/*
2** File: 3c503.c Dec. 20, 1996
3**
4** Author: Giovanni Falzoni <gfalzoni@inwind.it>
5**
6** Driver for the Etherlink II boards. Works in shared memory mode.
7** Programmed I/O could be used as well but would result in poor
8** performances. This file contains only the board specific code,
9** the rest is in 8390.c Code specific for ISA bus only
10**
11** $Id: 3c503.c,v 1.3 2005/08/05 19:08:43 beng Exp $
12*/
13
14#include "drivers.h"
15#include <net/gen/ether.h>
16#include <net/gen/eth_io.h>
17#include "dp.h"
18
19#if (ENABLE_3C503 == 1)
20
21#include "8390.h"
22#include "3c503.h"
23
24/*
25** Name: void el2_init(dpeth_t *dep);
26** Function: Initalize hardware and data structures.
27*/
28static void el2_init(dpeth_t * dep)
29{
30 int ix, irq;
31 int sendq_nr;
32 int cntr;
33
34 /* Map the address PROM to lower I/O address range */
35 cntr = inb_el2(dep, EL2_CNTR);
36 outb_el2(dep, EL2_CNTR, cntr | ECNTR_SAPROM);
37
38 /* Read station address from PROM */
39 for (ix = EL2_EA0; ix <= EL2_EA5; ix += 1)
40 dep->de_address.ea_addr[ix] = inb_el2(dep, ix);
41
42 /* Map the 8390 back to lower I/O address range */
43 outb_el2(dep, EL2_CNTR, cntr);
44
45 /* Enable memory, but turn off interrupts until we are ready */
46 outb_el2(dep, EL2_CFGR, ECFGR_IRQOFF);
47
48 dep->de_data_port = dep->de_dp8390_port = dep->de_base_port;
49 dep->de_prog_IO = FALSE; /* Programmed I/O not yet available */
50
51 /* Check width of data bus */
52 outb_el2(dep, DP_CR, CR_PS_P0 | CR_NO_DMA | CR_STP);
53 outb_el2(dep, DP_DCR, 0);
54 outb_el2(dep, DP_CR, CR_PS_P2 | CR_NO_DMA | CR_STP);
55 dep->de_16bit = (inb_el2(dep, DP_DCR) & DCR_WTS) != 0;
56 outb_el2(dep, DP_CR, CR_PS_P0 | CR_NO_DMA | CR_STP);
57
58 /* Allocate one send buffer (1.5kb) per 8kb of on board memory. */
59 /* Only 8kb of 3c503/16 boards are used to avoid specific routines */
60 sendq_nr = dep->de_ramsize / 0x2000;
61 if (sendq_nr < 1)
62 sendq_nr = 1;
63 else if (sendq_nr > SENDQ_NR)
64 sendq_nr = SENDQ_NR;
65
66 dep->de_sendq_nr = sendq_nr;
67 for (ix = 0; ix < sendq_nr; ix++)
68 dep->de_sendq[ix].sq_sendpage = (ix * SENDQ_PAGES) + EL2_SM_START_PG;
69
70 dep->de_startpage = (ix * SENDQ_PAGES) + EL2_SM_START_PG;
71 dep->de_stoppage = EL2_SM_STOP_PG;
72
73 outb_el2(dep, EL2_STARTPG, dep->de_startpage);
74 outb_el2(dep, EL2_STOPPG, dep->de_stoppage);
75
76 /* Point the vector pointer registers somewhere ?harmless?. */
77 outb_el2(dep, EL2_VP2, 0xFF); /* Point at the ROM restart location */
78 outb_el2(dep, EL2_VP1, 0xFF); /* 0xFFFF:0000 (from original sources) */
79 outb_el2(dep, EL2_VP0, 0x00); /* - What for protected mode? */
80
81 /* Set interrupt level for 3c503 */
82 irq = (dep->de_irq &= ~DEI_DEFAULT); /* Strip the default flag. */
83 if (irq == 9) irq = 2;
84 if (irq < 2 || irq > 5) panic(dep->de_name, "bad 3c503 irq configuration", irq);
85 outb_el2(dep, EL2_IDCFG, (0x04 << irq));
86
87 outb_el2(dep, EL2_DRQCNT, 0x08); /* Set burst size to 8 */
88 outb_el2(dep, EL2_DMAAH, EL2_SM_START_PG); /* Put start of TX */
89 outb_el2(dep, EL2_DMAAL, 0x00); /* buffer in the GA DMA reg */
90
91 outb_el2(dep, EL2_CFGR, ECFGR_NORM); /* Enable shared memory */
92
93 ns_init(dep); /* Initialize DP controller */
94
95 printf("%s: Etherlink II%s (%s) at %X:%d:%05lX - ",
96 dep->de_name, dep->de_16bit ? "/16" : "", "3c503",
97 dep->de_base_port, dep->de_irq,
98 dep->de_linmem + dep->de_offset_page);
99 for (ix = 0; ix < SA_ADDR_LEN; ix += 1)
100 printf("%02X%c", dep->de_address.ea_addr[ix],
101 ix < SA_ADDR_LEN - 1 ? ':' : '\n');
102 return;
103}
104
105/*
106** Name: void el2_stop(dpeth_t *dep);
107** Function: Stops board by disabling interrupts.
108*/
109static void el2_stop(dpeth_t * dep)
110{
111
112 outb_el2(dep, EL2_CFGR, ECFGR_IRQOFF);
113 sys_irqdisable(&dep->de_hook); /* disable interrupts */
114 return;
115}
116
117/*
118** Name: void el2_probe(dpeth_t *dep);
119** Function: Probe for the presence of an EtherLink II card.
120** Initialize memory addressing if card detected.
121*/
122int el2_probe(dpeth_t * dep)
123{
124 int iobase, membase;
125 int thin;
126
127 /* Thin ethernet or AUI? */
128 thin = (dep->de_linmem & 1) ? ECNTR_AUI : ECNTR_THIN;
129
130 /* Location registers should have 1 bit set */
131 if (!(iobase = inb_el2(dep, EL2_IOBASE))) return FALSE;
132 if (!((membase = inb_el2(dep, EL2_MEMBASE)) & 0xF0)) return FALSE;
133 if ((iobase & (iobase - 1)) || (membase & (membase - 1))) return FALSE;
134
135 /* Resets board */
136 outb_el2(dep, EL2_CNTR, ECNTR_RESET | thin);
137 milli_delay(1);
138 outb_el2(dep, EL2_CNTR, thin);
139 milli_delay(5);
140
141 /* Map the address PROM to lower I/O address range */
142 outb_el2(dep, EL2_CNTR, ECNTR_SAPROM | thin);
143 if (inb_el2(dep, EL2_EA0) != 0x02 || /* Etherlink II Station address */
144 inb_el2(dep, EL2_EA1) != 0x60 || /* MUST be 02:60:8c:xx:xx:xx */
145 inb_el2(dep, EL2_EA2) != 0x8C)
146 return FALSE; /* No Etherlink board at this address */
147
148 /* Map the 8390 back to lower I/O address range */
149 outb_el2(dep, EL2_CNTR, thin);
150
151 /* Setup shared memory addressing for 3c503 */
152 dep->de_linmem = ((membase & 0xC0) ? EL2_BASE_0D8000 : EL2_BASE_0C8000) +
153 ((membase & 0xA0) ? (EL2_BASE_0CC000 - EL2_BASE_0C8000) : 0x0000);
154
155 /* Shared memory starts at 0x2000 (8kb window) */
156 dep->de_offset_page = (EL2_SM_START_PG * DP_PAGESIZE);
157 dep->de_linmem -= dep->de_offset_page;
158 dep->de_ramsize = (EL2_SM_STOP_PG - EL2_SM_START_PG) * DP_PAGESIZE;
159
160 /* Board initialization and stop functions */
161 dep->de_initf = el2_init;
162 dep->de_stopf = el2_stop;
163 return TRUE;
164}
165#endif /* ENABLE_3C503 */
166
167/** 3c503.c **/
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