| 1 | /*
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| 2 | ** File: 3c503.h Dec. 20, 1996
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| 3 | **
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| 4 | ** Author: Giovanni Falzoni <gfalzoni@inwind.it>
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| 5 | **
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| 6 | ** Interface description for 3Com Etherlink II boards
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| 7 | **
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| 8 | ** $Log: 3c503.h,v $
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| 9 | ** Revision 1.1 2005/06/29 10:16:46 beng
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| 10 | ** Import of dpeth 3c501/3c509b/.. ethernet driver by
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| 11 | ** Giovanni Falzoni <fgalzoni@inwind.it>.
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| 12 | **
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| 13 | ** Revision 2.0 2005/06/26 16:16:46 lsodgf0
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| 14 | ** Initial revision for Minix 3.0.6
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| 15 | **
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| 16 | ** $Id: 3c503.h,v 1.1 2005/06/29 10:16:46 beng Exp $
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| 17 | */
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| 18 |
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| 19 | #define EL2_MEMTEST 0 /* Set to 1 for on board memory test */
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| 20 |
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| 21 | #define EL2_GA 0x0400 /* Offset of registers in Gate Array */
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| 22 |
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| 23 | /* EtherLink II card */
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| 24 |
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| 25 | #define EL2_STARTPG (EL2_GA+0x00) /* Start page matching DP_PSTARTPG */
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| 26 | #define EL2_STOPPG (EL2_GA+0x01) /* Stop page matching DP_PSTOPPG */
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| 27 | #define EL2_DRQCNT (EL2_GA+0x02) /* DMA burst count */
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| 28 | #define EL2_IOBASE (EL2_GA+0x03) /* I/O base jumpers (bit coded) */
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| 29 | #define EL2_MEMBASE (EL2_GA+0x04) /* Memory base jumpers (bit coded) */
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| 30 | #define EL2_CFGR (EL2_GA+0x05) /* Configuration Register for GA */
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| 31 | #define EL2_CNTR (EL2_GA+0x06) /* Control(write) and status(read) */
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| 32 | #define EL2_STATUS (EL2_GA+0x07)
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| 33 | #define EL2_IDCFG (EL2_GA+0x08) /* Interrupt/DMA configuration reg */
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| 34 | #define EL2_DMAAH (EL2_GA+0x09) /* DMA address register (High byte) */
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| 35 | #define EL2_DMAAL (EL2_GA+0x0A) /* DMA address register (Low byte) */
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| 36 | #define EL2_VP2 (EL2_GA+0x0B) /* Vector pointer - set to */
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| 37 | #define EL2_VP1 (EL2_GA+0x0C) /* reset address (0xFFFF:0) */
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| 38 | #define EL2_VP0 (EL2_GA+0x0D) /* */
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| 39 | #define EL2_FIFOH (EL2_GA+0x0E) /* FIFO for progr. I/O (High byte) */
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| 40 | #define EL2_FIFOL (EL2_GA+0x0F) /* FIFO for progr. I/O (Low byte) */
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| 41 |
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| 42 | #define EL2_EA0 0x00 /* Most significant byte of ethernet address */
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| 43 | #define EL2_EA1 0x01
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| 44 | #define EL2_EA2 0x02
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| 45 | #define EL2_EA3 0x03
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| 46 | #define EL2_EA4 0x04
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| 47 | #define EL2_EA5 0x05 /* Least significant byte of ethernet address */
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| 48 |
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| 49 | /* Bits in EL2_CNTR register */
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| 50 | #define ECNTR_RESET 0x01 /* Software Reset */
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| 51 | #define ECNTR_THIN 0x02 /* Onboard transceiver enable */
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| 52 | #define ECNTR_AUI 0x00 /* Onboard transceiver disable */
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| 53 | #define ECNTR_SAPROM 0x04 /* Map the station address prom */
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| 54 |
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| 55 | /* Bits in EL2_CFGR register */
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| 56 | #define ECFGR_NORM 0x49 /* Enable 8k shared memory, no DMA, TC int */
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| 57 | #define ECFGR_IRQOFF 0xC9 /* As above, disable 8390 IRQ */
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| 58 |
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| 59 | /* Shared memory management parameters */
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| 60 | #define EL2_SM_START_PG 0x20 /* First page of TX buffer */
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| 61 | #define EL2_SM_STOP_PG 0x40 /* Last page +1 of RX ring */
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| 62 |
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| 63 | /* Physical addresses where an Etherlink board can be configured */
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| 64 | #define EL2_BASE_0C8000 0x0C8000
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| 65 | #define EL2_BASE_0CC000 0x0CC000
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| 66 | #define EL2_BASE_0D8000 0x0D8000
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| 67 | #define EL2_BASE_0DC000 0x0DC000
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| 68 |
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| 69 | #define inb_el2(dep,reg) (inb((dep)->de_base_port+(reg)))
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| 70 | #define outb_el2(dep,reg,data) (outb((dep)->de_base_port+(reg),(data)))
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| 71 |
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| 72 | /** 3c503.h **/
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