source: trunk/minix/drivers/fxp/fxp.h@ 10

Last change on this file since 10 was 9, checked in by Mattia Monga, 14 years ago

Minix 3.1.2a
File size: 20.0 KB
RevLine 
[9]1/*
2ibm/fxp.h
3
4Registers and datastructures of the Intel 82557, 82558, 82559, 82550,
5and 82562 fast ethernet controllers.
6
7Created: Nov 2004 by Philip Homburg <philip@f-mnx.phicoh.com>
8*/
9
10#define VERBOSE 0 /* display output during intialization */
11
12/* Revisions in PCI_REV */
13#define FXP_REV_82557A 0x01
14#define FXP_REV_82557B 0x02
15#define FXP_REV_82557C 0x03
16#define FXP_REV_82558A 0x04
17#define FXP_REV_82558B 0x05
18#define FXP_REV_82559A 0x06
19#define FXP_REV_82559B 0x07
20#define FXP_REV_82559C 0x08
21#define FXP_REV_82559ERA 0x09
22#define FXP_REV_82550_1 0x0C
23#define FXP_REV_82550_2 0x0D
24#define FXP_REV_82550_3 0x0E
25#define FXP_REV_82551_1 0x0F
26#define FXP_REV_82551_2 0x10
27
28/* Control/Status Registers (CSR). The first 8 bytes are called
29 * System Control Block (SCB)
30 */
31#define SCB_STATUS 0x00 /* Lower half of the SCB status word. CU and
32 * RU status.
33 */
34#define SS_CUS_MASK 0xC0 /* CU Status */
35#define SS_CU_IDLE 0x00 /* Idle */
36#define SS_CU_SUSP 0x40 /* Suspended */
37#define SS_CU_LPQA 0x80 /* LPQ Active */
38#define SS_CU_HQPA 0xC0 /* HQP Active */
39#define SS_RUS_MASK 0x3C /* RU Status */
40#define SS_RU_IDLE 0x00 /* Idle */
41#define SS_RU_SUSP 0x04 /* Suspended */
42#define SS_RU_NORES 0x08 /* No Resources */
43#define SS_RU_READY 0x10 /* Ready */
44 /* Other values are reserved */
45#define SS_RESERVED 0x03 /* Reserved */
46#define SCB_INT_STAT 0x01 /* Upper half of the SCB status word.
47 * Interrupt status. Also used to acknoledge
48 * interrupts.
49 */
50#define SIS_CX 0x80 /* CU command with interrupt bit set. On
51 * 82557 also TNO Interrupt.
52 */
53#define SIS_FR 0x40 /* Frame Received */
54#define SIS_CNA 0x20 /* CU Not Active */
55#define SIS_RNR 0x10 /* RU Not Ready */
56#define SIS_MDI 0x08 /* MDI read/write cycle completed */
57#define SIS_SWI 0x04 /* Software Interrupt */
58#define SIS_RES 0x02 /* Reserved */
59#define SIS_FCP 0x01 /* Flow Control Pause Interrupt (82558 and
60 * later, reserved on 82557)
61 */
62#define SCB_CMD 0x02 /* Lower half of the SCB command word. CU and
63 * RU commands.
64 */
65#define SC_CUC_MASK 0xF0
66#define SC_CU_NOP 0x00 /* NOP */
67#define SC_CU_START 0x10 /* Start CU */
68#define SC_CU_RESUME 0x20 /* Resume CU */
69#define SC_CU_LOAD_DCA 0x40 /* Load Dump Counters Address */
70#define SC_CU_DUMP_SC 0x50 /* Dump Statistical Counters */
71#define SC_CU_LOAD_BASE 0x60 /* Load CU Base */
72#define SC_CU_DUMP_RSET_SC 0x70 /* Dump and Reset Counters */
73#define SC_CU_STATIC_RESUME 0xA0 /* Static Resume, 82558 and
74 * above
75 */
76#define SC_RESERVED 0x08 /* Reserved */
77#define SC_RUC_MASK 0x07 /* RU Command Mask */
78#define SC_RU_NOP 0x00 /* NOP */
79#define SC_RU_START 0x01 /* Start RU */
80#define SC_RU_RESUME 0x02 /* Resume RU */
81#define SC_RU_DMA_REDIR 0x03 /* DMA Redirect */
82#define SC_RU_ABORT 0x04 /* Abort RU */
83#define SC_RU_LOAD_HDR 0x05 /* Load Header Data Size */
84#define SC_RU_LOAD_BASE 0x06 /* Load RU Base */
85#define SCB_INT_MASK 0x03 /* Upper half of the SCB command word.
86 * Interrupt mask. Can also be used to
87 * generate a 'software' interrupt.
88 */
89 /* The following 6 mask bits are not valid on
90 * the 82557.
91 */
92#define SIM_CX 0x80 /* Mask CX */
93#define SIM_FR 0x40 /* Mask FR */
94#define SIM_CNA 0x20 /* Mask CNA */
95#define SIM_RNR 0x10 /* Mask RNR */
96#define SIM_ER 0x08 /* Mask ER */
97#define SIM_FCP 0x04 /* Mask FCP */
98#define SIM_SI 0x02 /* Generate Software Interrupt */
99#define SIM_M 0x01 /* Mask all interrupts */
100#define SCB_POINTER 0x04 /* A 32-bit (pointer) argument for CU and RU
101 * commands.
102 */
103#define CSR_PORT 0x08 /* Control functions that bypass the SCB */
104#define CP_PTR_MASK 0xFFFFFFF0 /* Argument pointer */
105#define CP_CMD_MASK 0x0000000F /* Commands bits */
106#define CP_CMD_SOFT_RESET 0x00000000 /* Software reset */
107#define CSR_PORT_RESET_DELAY 10 /* Wait for reset to
108 * complete. In micro
109 * seconds.
110 */
111#define CP_CMD_SELF_TEST 0x00000001 /* Self test */
112#define CP_CMD_SEL_RESET 0x00000002 /* Selective reset */
113#define CP_CMD_DUMP 0x00000003 /* Dump */
114#define CP_CMD_DUMP_WAKEUP 0x00000007 /* Dump and wake-up,
115 * 82559 and later.
116 */
117#define CSR_RESERVED 0x0C /* reserved, 16-bits */
118#define CSR_EEPROM 0x0E /* EEPROM Control Register */
119#define CE_RESERVED 0xF0 /* Reserved */
120#define CE_EEDO 0x08 /* Serial Data Out (of the EEPROM) */
121#define CE_EEDI 0x04 /* Serial Data In (to the EEPROM) */
122#define CE_EECS 0x02 /* Chip Select */
123#define CE_EESK 0x01 /* Serial Clock */
124#define CSR_RESERVED1 0x0F /* Reserved */
125#define CSR_MDI_CTL 0x10 /* MDI Control Register, 32-bits */
126#define CM_RESERVED 0xC0000000 /* Reserved */
127#define CM_IE 0x20000000 /* Enable Interrupt */
128#define CM_READY 0x10000000 /* Command completed */
129#define CM_OPCODE_MASK 0x0C000000 /* Opcode */
130#define CM_WRITE 0x04000000 /* Write */
131#define CM_READ 0x08000000 /* Read */
132#define CM_PHYADDR_MASK 0x03E00000 /* Which PHY */
133#define CM_PHYADDR_SHIFT 21
134#define CM_REG_MASK 0x001F0000 /* Which register in the PHY */
135#define CM_REG_SHIFT 16
136#define CM_DATA_MASK 0x0000FFFF /* Data to be read or written */
137
138/* Control Block List (CBL) commands */
139#define CBL_NOP 0 /* No-operation */
140#define CBL_AIS 1 /* Individual Address Setup */
141#define CBL_CONF 2 /* Configure NIC */
142#define CBL_MAS 3 /* Multicast Address Setup */
143#define CBL_XMIT 4 /* Transmit */
144#define CBL_LM 5 /* Load Microcode */
145#define CBL_DUMP 6 /* Dump Internal Registers */
146#define CBL_DIAG 7 /* Diagnose Command */
147
148/* Common command fields */
149#define CBL_C_CMD_MASK 0x0007 /* Command bits */
150#define CBL_C_EL 0x8000 /* End of CBL */
151#define CBL_C_S 0x4000 /* Suspend after the completion of the CB */
152#define CBL_C_I 0x2000 /* Request CX Interrupt */
153#define CBL_C_RES 0x1FF8 /* Reserved */
154
155/* Command flags */
156#define CBL_F_C 0x8000 /* Command has completed */
157#define CBL_F_RES1 0x4000 /* Reserved */
158#define CBL_F_OK 0x2000 /* Command was executed without errors */
159#define CBL_F_RES0 0x1FFF /* Reserved */
160
161/* Individual Address Setup (1) */
162struct ias
163{
164 u16_t ias_status;
165 u16_t ias_command;
166 u32_t ias_linkaddr;
167 u8_t ias_ethaddr[6];
168 u8_t ias_reserved[2];
169};
170
171/* Configure (2) */
172#define CC_BYTES_NR 22 /* Number of configuration bytes */
173struct cbl_conf
174{
175 u16_t cc_status;
176 u16_t cc_command;
177 u32_t cc_linkaddr;
178 u8_t cc_bytes[CC_BYTES_NR];
179};
180
181/* Byte 0 */
182#define CCB0_RES 0xC0 /* Reserved (0) */
183#define CCB0_BYTECOUNT 0x3F /* Byte Count (typically either 8 or 22) */
184
185/* Byte 1 */
186#define CCB1_RES 0x80 /* Reserved (0) */
187#define CCB1_TXFIFO_LIM 0x70 /* Transmit FIFO Limit, in DWORDS */
188#define CTL_DEFAULT 0x00 /* 0 bytes */
189#define CCB1_RXFIFO_LIM 0x0F /* Receive FIFO Limit */
190#define CRL_DEFAULT 0x08 /* 32 bytes on 82557, 64 bytes on
191 * 82558/82559.
192 */
193
194/* Byte 2 */
195#define CCB2_AIFS 0xFF /* Adaptive IFS */
196#define CAI_DEFAULT 0
197
198/* Byte 3 */
199 /* Reserved (must be 0) on 82557 */
200#define CCB3_RES 0xF0 /* Reserved (0) */
201#define CCB3_TWCL 0x08 /* Terminate Write on Cache Line */
202#define CCB3_RAE 0x04 /* Read Alignment Enable */
203#define CCB3_TE 0x02 /* Type Enable??? */
204#define CCB3_MWIE 0x01 /* Memory Write and Invalidate (MWI) Enable
205 * Additionally the MWI bit in the PCI
206 * command register has to be set.
207 * Recommended by Intel.
208 */
209
210/* Byte 4 */
211#define CCB4_RES 0x80 /* Reserved (0) */
212#define CCB4_RXDMA_MAX 0x7F /* Receive DMA Maximum Byte Count */
213
214/* Byte 5 */
215#define CCB5_DMBCE 0x80 /* DMA Maximum Byte Count Enable */
216#define CCB5_TXDMA_MAX 0x7F /* Transmit DMA Maximum Byte Count */
217
218/* Byte 6 */
219#define CCB6_SBF 0x80 /* Save Bad Frames */
220#define CCB6_DORF 0x40 /* (Do not) Discard Overrun Receive Frame,
221 * Set this bit to keep them.
222 */
223#define CCB6_ESC 0x20 /* Extended Statistical Counter. Reserved
224 * on 82557, must be set to 1.
225 * Clear this bit to get more counters.
226 */
227#define CCB6_ETCB 0x10 /* Extended Transmit CB. Reserved on 82557,
228 * must be set to 1.
229 * Clear this bit to use Extended TxCBs.
230 */
231#define CCB6_CI_INT 0x08 /* CPU Idle (CI) Interrupt. Generate a
232 * CI Int (bit set) or a CNA Int (bit clear)
233 * when the CU goes to the idle state (or
234 * to suspended for CNA).
235 */
236#define CCB6_TNO_INT 0x04 /* Enable TNO Interrupt (82557 only) */
237#define CCB6_TCOSC 0x04 /* TCO Statistical Counter (82559 only) */
238#define CCB6_RES 0x02 /* Reserved, must be set to 1. Called "disable
239 * direct rcv dma mode" by the FreeBSD
240 * driver.
241 */
242#define CCB6_LSCB 0x01 /* Late SCB Update. Only on 82557. */
243
244/* Byte 7 */
245#define CCB7_DTBD 0x80 /* Dynamic TBD. Reserved on 82557, should be
246 * be set to 0.
247 */
248#define CCB7_2FFIFO 0x40 /* (At Most) Two Frames in FIFO. Reserved on
249 * 82557, should be set to 0.
250 */
251#define CCB7_RES 0x38 /* Reserved (0) */
252#define CCB7_UR 0x06 /* Underrun Retry */
253#define CUR_0 0x00 /* No re-transmission */
254#define CUR_1 0x02 /* One re-transmission */
255#define CUR_2 0x04 /* Two re-transmissions, 1st retry with
256 * 512 bytes.
257 */
258#define CUR_3 0x06 /* Tree re-transmissions, 1st retry
259 * with 512 bytes, 2nd retry with 1024.
260 */
261#define CCB7_DSRF 0x01 /* Discard Short Receive Frames. */
262
263/* Byte 8 */
264#define CCB8_CSMAD 0x80 /* CSMA Disable. Reserved on 82557, should be
265 * set to zero.
266 */
267#define CCB8_RES 0x7E /* Reserved (0) */
268#define CCB8_503_MII 0x01 /* 503 mode or MII mode. Reserved on 82558
269 * and 82559, should be set to 1.
270 */
271
272/* Byte 9 */
273#define CCB9_MMWE 0x80 /* Multicast Match Wake Enable. 82558 B-step
274 * only, should be set to zero on other
275 * devices.
276 */
277#define CCB9_AWE 0x40 /* ARP Wake-up Enable. 82558 B-step only,
278 * should be set to zero on other devices.
279 */
280#define CCB9_LSCWE 0x20 /* Link Status Change Wake Enable. Available
281 * on 82558 B-step and 82559. Should be
282 * set to zero on 82557 and 82558 A-step
283 */
284#define CCB9_VARP 0x10 /* VLAN ARP (82558 B-step) or VLAN TCO (82559).
285 * Should be zero on 82557 and 82558 A-step
286 */
287#define CCB9_RES 0x0E /* Reserved (0) */
288#define CCB9_TUC 0x01 /* TCP/UDP Checksum. 82559 only, should be
289 * zero on other devices.
290 */
291
292/* Byte 10 */
293#define CCB10_LOOPBACK 0xC0 /* Loopback mode */
294#define CLB_NORMAL 0x00 /* Normal operation */
295#define CLB_INTERNAL 0x40 /* Internal loopback */
296#define CLB_RESERVED 0x80 /* Reserved */
297#define CLB_EXTERNAL 0xC0 /* External loopback */
298#define CCB10_PAL 0x30 /* Pre-amble length */
299#define CPAL_1 0x00 /* 1 byte */
300#define CPAL_3 0x10 /* 3 bytes */
301#define CPAL_7 0x20 /* 7 bytes */
302#define CPAL_15 0x30 /* 15 bytes */
303#define CPAL_DEFAULT CPAL_7
304#define CCB10_NSAI 0x08 /* No Source Address Insertion */
305#define CCB10_RES1 0x06 /* Reserved, should be set to 1 */
306#define CCB10_RES0 0x01 /* Reserved (0) */
307
308/* Byte 11 */
309#define CCB11_RES 0xF8 /* Reserved (0) */
310#define CCB11_LINPRIO 0x07 /* Linear Priority. 82557 only,
311 * should be zero on other devices.
312 */
313
314/* Byte 12 */
315#define CCB12_IS 0xF0 /* Interframe spacing in multiples of
316 * 16 bit times.
317 */
318#define CIS_DEFAULT 0x60 /* 96 (6 in register) */
319#define CCB12_RES 0x0E /* Reserved (0) */
320#define CCB12_LPM 0x01 /* Linear Priority Mode. 82557 only,
321 * should be zero on other devices.
322 */
323
324/* Byte 13, 4th byte of IP address for ARP frame filtering. Only valid on
325 * 82558 B-step. Should be 0 on other devices.
326 */
327#define CCB13_DEFAULT 0x00
328/* Byte 14, 3rd byte of IP address for ARP fram efiltering. Only valid on
329 * 82558 B-step. Should be 0xF2 on other devices.
330 */
331#define CCB14_DEFAULT 0xF2
332
333/* Byte 15 */
334#define CCB15_CRSCDT 0x80 /* CRS or CDT. */
335#define CCB15_RES1 0x40 /* Reserved, should be set to one. */
336#define CCB15_CRC16 0x20 /* 16-bit CRC. Only on 82559,
337 * should be zero on other devices
338 */
339#define CCB15_IUL 0x10 /* Ignore U/L. Reserved on 82557 and
340 * should be set to zero.
341 */
342#define CCB15_RES2 0x08 /* Reserved, should be set to one. */
343#define CCB15_WAW 0x04 /* Wait After Win. Reserved on 82557,
344 * should be set to zero.
345 */
346#define CCB15_BD 0x02 /* Broadcast disable */
347#define CCB15_PM 0x01 /* Promiscuous mode */
348
349/* Byte 16. FC Delay Least Significant Byte. Reserved on the 82557 and
350 * should be set to zero.
351 */
352#define CCB16_DEFAULT 0x00
353
354/* Byte 17. FC Delay Most Significant Byte. This byte is reserved on the
355 * 82557 and should be set to 0x40.
356 */
357#define CCB17_DEFAULT 0x40
358
359/* Byte 18 */
360#define CCB18_RES1 0x80 /* Reserved, should be set to 1 */
361#define CCB18_PFCT 0x70 /* Priority Flow Control Threshold.
362 * Reserved on the 82557 and should
363 * be set to 1. All bits 1 (disabled)
364 * is the recommended default.
365 */
366#define CCB18_LROK 0x08 /* Long Receive OK. Reserved on the
367 * 82557 and should be set to zero.
368 * Required for VLANs.
369 */
370#define CCB18_RCRCT 0x04 /* Receive CRC Transfer */
371#define CCB18_PE 0x02 /* Padding Enable */
372#define CCB18_SE 0x01 /* Stripping Enable */
373
374/* Byte 19 */
375#define CCB19_FDPE 0x80 /* Full Duplex Pin Enable */
376#define CCB19_FFD 0x40 /* Force Full Duplex */
377#define CCB19_RFC 0x20 /* Reject FC. Reserved on the 82557
378 * and should be set to zero.
379 */
380#define CCB19_FDRSTAFC 0x10 /* Full Duplex Restart Flow Control.
381 * Reserved on the 82557 and should be
382 * set to zero.
383 */
384#define CCB19_FDRSTOFC 0x08 /* Full Duplex Restop Flow Control.
385 * Reserved on the 82557 and should be
386 * set to zero.
387 */
388#define CCB19_FDTFCD 0x04 /* Full Duplex Transmit Flow Control
389 * Disable. Reserved on the 82557 and
390 * should be set to zero.
391 */
392#define CCB19_MPWD 0x02 /* Magic Packet Wake-up Disable.
393 * Reserved on the 82557 and 82559ER
394 * and should be set to zero.
395 */
396#define CCB19_AW 0x01 /* Address Wake-up (82558 A-step) and
397 * IA Match Wake Enable (82558 B-step)
398 * Reserved on the 82557 and 82559 and
399 * should be set to zero.
400 */
401
402/* Byte 20 */
403#define CCB20_RES 0x80 /* Reserved (0) */
404#define CCB20_MIA 0x40 /* Multiple IA */
405#define CCB20_PFCL 0x20 /* Priority FC Location. Reserved on
406 * the 82557 and should be set to 1.
407 */
408#define CCB20_RES1 0x1F /* Reserved, should be set to 1 */
409
410/* Byte 21 */
411#define CCB21_RES 0xF0 /* Reserved (0) */
412#define CCB21_MA 0x08 /* Multicast All */
413#define CCB21_RES1_MASK 0x07 /* Reserved, should be set to 5 */
414#define CCB21_RES21 0x05
415
416/* Transmit (4) */
417struct tx
418{
419 u16_t tx_status;
420 u16_t tx_command;
421 u32_t tx_linkaddr;
422 u32_t tx_tbda;
423 u16_t tx_size;
424 u8_t tx_tthresh;
425 u8_t tx_ntbd;
426 u8_t tx_buf[ETH_MAX_PACK_SIZE_TAGGED];
427};
428
429#define TXS_C 0x8000 /* Transmit DMA has completed */
430#define TXS_RES 0x4000 /* Reserved */
431#define TXS_OK 0x2000 /* Command was executed without error */
432#define TXS_U 0x1000 /* This or previous frame encoutered underrun */
433#define TXS_RES1 0x0FFF /* Reserved (0) */
434
435#define TXC_EL 0x8000 /* End of List */
436#define TXC_S 0x4000 /* Suspend after this CB */
437#define TXC_I 0x2000 /* Interrupt after this CB */
438#define TXC_CID_MASK 0x1F00 /* CNA Interrupt Delay */
439#define TXC_RES 0x00E0 /* Reserved (0) */
440#define TXC_NC 0x0010 /* No CRC and Source Address Insertion */
441#define TXC_SF 0x0008 /* Not in Simplified Mode */
442#define TXC_CMD 0x0007 /* Command */
443
444#define TXSZ_EOF 0x8000 /* End of Frame */
445#define TXSZ_RES 0x4000 /* Reserved (0) */
446#define TXSZ_COUNT 0x3FFF /* Transmit Byte Count */
447
448#define TX_TBDA_NIL 0xFFFFFFFF /* Null Pointer for TBD Array */
449
450#define TXTT_MIN 0x01 /* Minimum for Transmit Threshold */
451#define TXTT_MAX 0xE0 /* Maximum for Transmit Threshold */
452
453/* Statistical Counters */
454struct sc
455{
456 u32_t sc_tx_good; /* Transmit Good Frames */
457 u32_t sc_tx_maxcol; /* Transmit Maximum Collisions errors */
458 u32_t sc_tx_latecol; /* Transmit Late Collisions errors */
459 u32_t sc_tx_underrun; /* Transmit Underrun errors */
460 u32_t sc_tx_crs; /* Transmit Lost Carrier Sense */
461 u32_t sc_tx_defered; /* Transmit Defered */
462 u32_t sc_tx_scol; /* Transmit Single Collision */
463 u32_t sc_tx_mcol; /* Transmit Multiple Collisions */
464 u32_t sc_tx_totcol; /* Transmit Total Collisions */
465 u32_t sc_rx_good; /* Receive Good Frames */
466 u32_t sc_rx_crc; /* Receive CRC errors */
467 u32_t sc_rx_align; /* Receive Alignment errors */
468 u32_t sc_rx_resource; /* Receive Resource errors */
469 u32_t sc_rx_overrun; /* Receive Overrun errors */
470 u32_t sc_rx_cd; /* Receive Collision Detect errors */
471 u32_t sc_rx_short; /* Receive Short Frame errors */
472
473 /* Short form ends here. The magic number will
474 * be stored in the next field.
475 */
476
477 u32_t sc_tx_fcp; /* Transmit Flow Control Pause */
478 u32_t sc_rx_fcp; /* Receive Flow Control Pause */
479 u32_t sc_rx_fcu; /* Receive Flow Control Unsupported */
480
481 /* Longer form (82558 and later) ends here.
482 * The magic number will be stored in the
483 * next field.
484 */
485
486 u32_t sc_tx_tco; /* Transmit TCO frames */
487 u32_t sc_rx_tco; /* Receive TCO frames */
488 u32_t sc_magic; /* Dump of counters completed */
489};
490
491#define SCM_DSC 0x0000A005 /* Magic for SC_CU_DUMP_SC command */
492#define SCM_DRSC 0x0000A007 /* Magic for SC_CU_DUMP_RSET_SC cmd */
493
494/* Receive Frame Descriptor (RFD) */
495struct rfd
496{
497 u16_t rfd_status;
498 u16_t rfd_command;
499 u32_t rfd_linkaddr;
500 u32_t rfd_reserved;
501 u16_t rfd_res;
502 u16_t rfd_size;
503 u8_t rfd_buf[ETH_MAX_PACK_SIZE_TAGGED];
504};
505
506#define RFDS_C 0x8000 /* Frame Reception Completed */
507#define RFDS_RES 0x4000 /* Reserved (0) */
508#define RFDS_OK 0x2000 /* Frame received without any errors */
509#define RFDS_RES1 0x1000 /* Reserved */
510#define RFDS_CRCERR 0x0800 /* CRC error */
511#define RFDS_ALIGNERR 0x0400 /* Alignment error */
512#define RFDS_OUTOFBUF 0x0200 /* Ran out of buffer space (frame is frager
513 * than supplied buffer).
514 */
515#define RFDS_DMAOVR 0x0100 /* DMA overrun failure */
516#define RFDS_TOOSHORT 0x0080 /* Frame Too Short */
517#define RFDS_RES2 0x0040 /* Reserved */
518#define RFDS_TYPED 0x0020 /* Frame Is Typed (Type/Length field is 0 or
519 * >1500)
520 */
521#define RFDS_RXERR 0x0010 /* Receive Error */
522#define RFDS_RES3 0x0008 /* Reserved */
523#define RFDS_NOAM 0x0004 /* No Address Match */
524#define RFDS_NOAIAM 0x0002 /* No IA Address Match */
525#define RFDS_RXCOL 0x0001 /* Collition Detected During Reception (82557
526 * and 82558 only)
527 */
528#define RFDS_TCO 0x0001 /* TCO Packet (82559 and later) */
529
530#define RFDC_EL 0x8000 /* End of List */
531#define RFDC_S 0x4000 /* Suspend */
532#define RFDC_RES 0x3FE0 /* Reserved (0) */
533#define RFDC_H 0x0010 /* Header RFD */
534#define RFDC_SF 0x0008 /* (Not) Simplified Mode */
535#define RFDC_RES1 0x0007 /* Reserved (0) */
536
537#define RFDR_EOF 0x8000 /* End of Frame (all data is in the buffer) */
538#define RFDR_F 0x4000 /* Finished updating the count field */
539#define RFDR_COUNT 0x3FFF /* Actual Count */
540
541#define RFDSZ_RES 0xC000 /* Reserved (0) */
542#define RFDSZ_SIZE 0x3FFF /* Buffer Size */
543
544/* EEPROM commands */
545#define EEPROM_READ_PREFIX 0x6 /* Read command */
546#define EEPROM_PREFIX_LEN 3 /* Start bit and two command bits */
547
548/* EEPROM timing parameters */
549#define EECS_DELAY 1 /* Keep EECS low for at least EECS_DELAY
550 * microseconds
551 */
552#define EESK_PERIOD 4 /* A cycle of driving EESK high followed by
553 * driving EESK low should take at least
554 * EESK_PERIOD microseconds
555 */
556
557/* Special registers in the 82555 (and compatible) PHYs. Should be moved
558 * to a separate file if other drivers need this too.
559 */
560#define MII_SCR 0x10 /* Status and Control Register */
561#define MII_SCR_FC 0x8000 /* Flow Control */
562#define MII_SCR_T4E 0x4000 /* Enable T4 unless auto-negotiation */
563#define MII_SCR_CRSDC 0x2000 /* RX100 CRS Disconnect */
564#define MII_SCR_RES 0x1000 /* Reserved */
565#define MII_SCR_RCVSYNC 0x0800 /* RCV De-Serializer in sync */
566#define MII_SCR_100DOWN 0x0400 /* 100Base-T Power Down */
567#define MII_SCR_10DOWN 0x0200 /* 10Base-T Power Down */
568#define MII_SCR_POLARITY 0x0100 /* 10Base-T Polarity */
569#define MII_SCR_RES_1 0x00F8 /* Reserved */
570#define MII_SCR_T4 0x0004 /* 100Base-T4 negotiated */
571#define MII_SCR_100 0x0002 /* 100 Mbps negotiated */
572#define MII_SCR_FD 0x0001 /* Full Duplex negotiated */
573
574/*
575 * $PchId: fxp.h,v 1.1 2004/11/23 14:34:03 philip Exp $
576 */
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