| [9] | 1 | /*
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| 2 | ibm/rtl8139.h
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| 3 |
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| 4 | Created: Aug 2003 by Philip Homburg <philip@cs.vu.nl>
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| 5 | */
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| 6 |
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| 7 | #define RL_IDR 0x00 /* Ethernet address
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| 8 | * Note: RL_9346CR_EEM_CONFIG mode is
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| 9 | * required the change the ethernet
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| 10 | * address.
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| 11 | * Note: 4-byte write access only.
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| 12 | */
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| 13 | #define RL_N_TX 4 /* Number of transmit buffers */
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| 14 | #define RL_TSD0 0x010 /* Transmit Status of Descriptor 0 */
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| 15 | #define RL_TSD_CRS 0x80000000 /* Carrier Sense Lost */
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| 16 | #define RL_TSD_TABT 0x40000000 /* Transmit Abort */
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| 17 | #define RL_TSD_OWC 0x20000000 /* Out of Window Collision */
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| 18 | #define RL_TSD_CDH 0x10000000 /* CD Heart Beat */
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| 19 | #define RL_TSD_NCC_M 0x0F000000 /* Number of Collision Count */
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| 20 | #define RL_TSD_RES 0x00C00000 /* Reserved */
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| 21 | #define RL_TSD_ERTXTH_M 0x003F0000 /* Early Tx Threshold */
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| 22 | #define RL_TSD_ERTXTH_S 16 /* shift */
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| 23 | #define RL_TSD_ERTXTH_8 0x00000000 /* 8 bytes */
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| 24 | #define RL_TSD_TOK 0x00008000 /* Transmit OK */
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| 25 | #define RL_TSD_TUN 0x00004000 /* Transmit FIFO Underrun */
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| 26 | #define RL_TSD_OWN 0x00002000 /* Controller (does not) Own Buf. */
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| 27 | #define RL_TSD_SIZE 0x00001FFF /* Descriptor Size */
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| 28 | #define RL_TSAD0 0x20 /* Transmit Start Address of Descriptor 0 */
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| 29 | #define RL_RBSTART 0x30 /* Receive Buffer Start Address */
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| 30 | #define RL_CR 0x37 /* Command Register */
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| 31 | #define RL_CR_RES0 0xE0 /* Reserved */
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| 32 | #define RL_CR_RST 0x10 /* Reset */
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| 33 | #define RL_CR_RE 0x08 /* Receiver Enable */
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| 34 | #define RL_CR_TE 0x04 /* Transmitter Enable *
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| 35 | * Note: start with transmit buffer
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| 36 | * 0 after RL_CR_TE has been reset.
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| 37 | */
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| 38 | #define RL_CR_RES1 0x02 /* Reserved */
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| 39 | #define RL_CR_BUFE 0x01 /* Receive Buffer Empty */
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| 40 | #define RL_CAPR 0x38 /* Current Address of Packet Read */
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| 41 | #define RL_CAPR_DATA_OFF 0x10 /* Packet Starts at Offset */
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| 42 | #define RL_CBR 0x3A /* Current Buffer Address */
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| 43 | #define RL_IMR 0x3C /* Interrupt Mask Register */
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| 44 | #define RL_IMR_SERR 0x8000 /* System Error */
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| 45 | #define RL_IMR_TIMEOUT 0x4000 /* Time Out */
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| 46 | #define RL_IMR_LENCHG 0x2000 /* Cable Length Change */
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| 47 | #define RL_IMR_RES 0x1F80 /* Reserved */
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| 48 | #define RL_IMR_FOVW 0x0040 /* Rx FIFO Overflow */
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| 49 | #define RL_IMR_PUN 0x0020 /* Packet Underrun / Link Change */
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| 50 | #define RL_IMR_RXOVW 0x0010 /* Rx Buffer Overflow */
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| 51 | #define RL_IMR_TER 0x0008 /* Transmit Error */
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| 52 | #define RL_IMR_TOK 0x0004 /* Transmit OK */
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| 53 | #define RL_IMR_RER 0x0002 /* Receive Error */
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| 54 | #define RL_IMR_ROK 0x0001 /* Receive OK */
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| 55 | #define RL_ISR 0x3E /* Interrupt Status Register */
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| 56 | #define RL_ISR_SERR 0x8000 /* System Error */
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| 57 | #define RL_ISR_TIMEOUT 0x4000 /* Time Out */
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| 58 | #define RL_ISR_LENCHG 0x2000 /* Cable Length Change */
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| 59 | #define RL_ISR_RES 0x1F80 /* Reserved */
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| 60 | #define RL_ISR_FOVW 0x0040 /* Rx FIFO Overflow */
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| 61 | #define RL_ISR_PUN 0x0020 /* Packet Underrun / Link Change */
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| 62 | #define RL_ISR_RXOVW 0x0010 /* Rx Buffer Overflow */
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| 63 | #define RL_ISR_TER 0x0008 /* Transmit Error */
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| 64 | #define RL_ISR_TOK 0x0004 /* Transmit OK */
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| 65 | #define RL_ISR_RER 0x0002 /* Receive Error */
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| 66 | #define RL_ISR_ROK 0x0001 /* Receive OK */
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| 67 | #define RL_TCR 0x40 /* Transmit Configuration Register
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| 68 | * Note: RL_CR_TE has to be set to
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| 69 | * set/change RL_TCR.
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| 70 | */
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| 71 | #define RL_TCR_RES0 0x80000000 /* Reserved */
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| 72 | #define RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */
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| 73 | #define RL_TCR_IFG_M 0x03000000 /* Interframe Gap Time */
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| 74 | #define RL_TCR_IFG_STD 0x03000000 /* IEEE 802.3 std */
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| 75 | #if 0
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| 76 | #undef RL_TCR_IFG_STD
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| 77 | #define RL_TCR_IFG_STD 0x00000000
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| 78 | #endif
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| 79 | #define RL_TCR_HWVER_BM 0x00C00000 /* Hardware Version ID B */
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| 80 | #define RL_TCR_HWVER_RTL8139 0x60000000 /* RTL8139 */
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| 81 | #define RL_TCR_HWVER_RTL8139A 0x70000000 /* RTL8139A */
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| 82 | #define RL_TCR_HWVER_RTL8139AG 0x74000000 /* RTL8139A-G */
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| 83 | #define RL_TCR_HWVER_RTL8139B 0x78000000 /* RTL8139B */
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| 84 | #define RL_TCR_HWVER_RTL8130 0x78000000 /* RTL8130 (dup) */
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| 85 | #define RL_TCR_HWVER_RTL8139C 0x74000000 /* RTL8139C (dup) */
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| 86 | #define RL_TCR_HWVER_RTL8100 0x78800000 /* RTL8100 */
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| 87 | #define RL_TCR_HWVER_RTL8100B 0x74400000 /* RTL8100B /
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| 88 | RTL8139D */
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| 89 | #define RL_TCR_HWVER_RTL8139CP 0x74800000 /* RTL8139C+ */
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| 90 | #define RL_TCR_HWVER_RTL8101 0x74C00000 /* RTL8101 */
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| 91 | #define RL_TCR_RES1 0x00380000 /* Reserved */
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| 92 | #define RL_TCR_LBK_M 0x00060000 /* Loopback Test */
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| 93 | #define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */
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| 94 | #define RL_TCR_LBK_LOOKBOCK 0x00060000 /* Loopback Mode */
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| 95 | #define RL_TCR_CRC 0x00010000 /* (Do not) Append CRC */
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| 96 | #define RL_TCR_RES2 0x0000F800 /* Reserved */
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| 97 | #define RL_TCR_MXDMA_M 0x00000700 /* Max DMA Burst Size Tx */
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| 98 | #define RL_TCR_MXDMA_16 0x00000000 /* 16 bytes */
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| 99 | #define RL_TCR_MXDMA_32 0x00000100 /* 32 bytes */
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| 100 | #define RL_TCR_MXDMA_64 0x00000200 /* 64 bytes */
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| 101 | #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
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| 102 | #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
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| 103 | #define RL_TCR_MXDMA_256 0x00000400 /* 256 bytes */
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| 104 | #define RL_TCR_MXDMA_512 0x00000500 /* 512 bytes */
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| 105 | #define RL_TCR_MXDMA_1024 0x00000600 /* 1024 bytes */
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| 106 | #define RL_TCR_MXDMA_2048 0x00000700 /* 2048 bytes */
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| 107 | #define RL_TCR_TXRR_M 0x000000F0 /* Tx Retry Count */
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| 108 | #define RL_TCR_RES3 0x0000000E /* Reserved */
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| 109 | #define RL_TCR_CLRABT 0x00000001 /* Clear Abort */
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| 110 | #define RL_RCR 0x44 /* Receive Configuration Register
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| 111 | * Note: RL_CR_RE has to be set to
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| 112 | * set/change RL_RCR.
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| 113 | */
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| 114 | #define RL_RCR_RES0 0xF0000000 /& Reserved */
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| 115 | #define RL_RCR_ERTH_M 0x0F000000 /* Early Rx Threshold */
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| 116 | #define RL_RCR_ERTH_0 0x00000000 /* No threshold */
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| 117 | #define RL_RCR_ERTH_1 0x01000000 /* 1/16 */
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| 118 | #define RL_RCR_ERTH_2 0x02000000 /* 2/16 */
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| 119 | #define RL_RCR_ERTH_3 0x03000000 /* 3/16 */
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| 120 | #define RL_RCR_ERTH_4 0x04000000 /* 4/16 */
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| 121 | #define RL_RCR_ERTH_5 0x05000000 /* 5/16 */
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| 122 | #define RL_RCR_ERTH_6 0x06000000 /* 6/16 */
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| 123 | #define RL_RCR_ERTH_7 0x07000000 /* 7/16 */
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| 124 | #define RL_RCR_ERTH_8 0x08000000 /* 8/16 */
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| 125 | #define RL_RCR_ERTH_9 0x09000000 /* 9/16 */
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| 126 | #define RL_RCR_ERTH_10 0x0A000000 /* 10/16 */
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| 127 | #define RL_RCR_ERTH_11 0x0B000000 /* 11/16 */
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| 128 | #define RL_RCR_ERTH_12 0x0C000000 /* 12/16 */
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| 129 | #define RL_RCR_ERTH_13 0x0D000000 /* 13/16 */
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| 130 | #define RL_RCR_ERTH_14 0x0E000000 /* 14/16 */
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| 131 | #define RL_RCR_ERTH_15 0x0F000000 /* 15/16 */
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| 132 | #define RL_RCR_RES1 0x00FC0000 /* Reserved */
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| 133 | #define RL_RCR_MULERINT 0x00020000 /* Multiple Early Int Select */
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| 134 | #define RL_RCR_RER8 0x00010000 /* Receive small error packet */
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| 135 | #define RL_RCR_RXFTH_M 0x0000E000 /* Rx FIFO Threshold */
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| 136 | #define RL_RCR_RXFTH_16 0x00000000 /* 16 bytes */
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| 137 | #define RL_RCR_RXFTH_32 0x00002000 /* 32 bytes */
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| 138 | #define RL_RCR_RXFTH_64 0x00004000 /* 64 bytes */
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| 139 | #define RL_RCR_RXFTH_128 0x00006000 /* 128 bytes */
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| 140 | #define RL_RCR_RXFTH_256 0x00008000 /* 256 bytes */
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| 141 | #define RL_RCR_RXFTH_512 0x0000A000 /* 512 bytes */
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| 142 | #define RL_RCR_RXFTH_1024 0x0000C000 /* 1024 bytes */
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| 143 | #define RL_RCR_RXFTH_UNLIM 0x0000E000 /* unlimited */
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| 144 | #define RL_RCR_RBLEM_M 0x00001800 /* Rx Buffer Length */
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| 145 | #define RL_RCR_RBLEN_8K 0x00000000 /* 8KB + 16 bytes */
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| 146 | #define RL_RCR_RBLEN_8K_SIZE (8*1024)
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| 147 | #define RL_RCR_RBLEN_16K 0x00000800 /* 16KB + 16 bytes */
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| 148 | #define RL_RCR_RBLEN_16K_SIZE (16*1024)
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| 149 | #define RL_RCR_RBLEN_32K 0x00001000 /* 32KB + 16 bytes */
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| 150 | #define RL_RCR_RBLEN_32K_SIZE (32*1024)
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| 151 | #define RL_RCR_RBLEN_64K 0x00001800 /* 64KB + 16 bytes */
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| 152 | #define RL_RCR_RBLEN_64K_SIZE (64*1024)
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| 153 | /* Note: the documentation for the RTL8139C(L) or
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| 154 | * for the RTL8139D(L) claims that the buffer should
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| 155 | * be 16 bytes larger. Multiples of 8KB are the
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| 156 | * correct values.
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| 157 | */
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| 158 | #define RL_RCR_MXDMA_M 0x00000700 /* Rx DMA burst size */
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| 159 | #define RL_RCR_MXDMA_16 0x00000000 /* 16 bytes */
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| 160 | #define RL_RCR_MXDMA_32 0x00000100 /* 32 bytes */
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| 161 | #define RL_RCR_MXDMA_64 0x00000200 /* 64 bytes */
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| 162 | #define RL_RCR_MXDMA_128 0x00000300 /* 128 bytes */
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| 163 | #define RL_RCR_MXDMA_256 0x00000400 /* 256 bytes */
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| 164 | #define RL_RCR_MXDMA_512 0x00000500 /* 512 bytes */
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| 165 | #define RL_RCR_MXDMA_1024 0x00000600 /* 1024 bytes */
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| 166 | #define RL_RCR_MXDMA_UNLIM 0x00000700 /* unlimited */
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| 167 | #define RL_RCR_WRAP 0x00000080 /* (Do not) Wrap on receive */
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| 168 | #define RL_RCR_RES2 0x00000040 /* EEPROM type? */
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| 169 | #define RL_RCR_AER 0x00000020 /* Accept Error Packets */
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| 170 | #define RL_RCR_AR 0x00000010 /* Accept Runt Packets */
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| 171 | #define RL_RCR_AB 0x00000008 /* Accept Broadcast Packets */
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| 172 | #define RL_RCR_AM 0x00000004 /* Accept Multicast Packets */
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| 173 | #define RL_RCR_APM 0x00000002 /* Accept Physical Match Packets */
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| 174 | #define RL_RCR_AAP 0x00000001 /* Accept All Packets */
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| 175 | #define RL_MPC 0x4c /* Missed Packet Counter */
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| 176 | #define RL_9346CR 0x50 /* 93C46 Command Register */
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| 177 | #define RL_9346CR_EEM_M 0xC0 /* Operating Mode */
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| 178 | #define RL_9346CR_EEM_NORMAL 0x00 /* Normal Mode */
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| 179 | #define RL_9346CR_EEM_AUTOLOAD 0x40 /* Load from 93C46 */
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| 180 | #define RL_9346CR_EEM_PROG 0x80 /* 93C46 Programming */
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| 181 | #define RL_9346CR_EEM_CONFIG 0xC0 /* Config Write Enable */
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| 182 | #define RL_9346CR_RES 0x30 /* Reserved */
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| 183 | #define RL_9346CR_EECS 0x08 /* EECS Pin */
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| 184 | #define RL_9346CR_EESK 0x04 /* EESK Pin */
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| 185 | #define RL_9346CR_EEDI 0x02 /* EEDI Pin */
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| 186 | #define RL_9346CR_EEDO 0x01 /* EEDO Pin */
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| 187 | #define RL_CONFIG0 0x51 /* Configuration Register 0 */
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| 188 | #define RL_CONFIG1 0x52 /* Configuration Register 1 */
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| 189 | #define RL_MSR 0x58 /* Media Status Register */
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| 190 | #define RL_MSR_TXFCE 0x80 /* Tx Flow Control Enable */
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| 191 | #define RL_MSR_RXFCE 0x40 /* Rx Flow Control Enable */
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| 192 | #define RL_MSR_RES 0x20 /* Reserved */
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| 193 | #define RL_MSR_AUXSTAT 0x10 /* Aux. Power Present */
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| 194 | #define RL_MSR_SPEED_10 0x08 /* In 10 Mbps mode */
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| 195 | #define RL_MSR_LINKB 0x04 /* link Failed */
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| 196 | #define RL_MSR_TXPF 0x02 /* Sent Pause Packet */
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| 197 | #define RL_MSR_RXPF 0x01 /* Received Pause Packet */
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| 198 | #define RL_CONFIG3 0x59 /* Configuration Register 3 */
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| 199 | #define RL_CONFIG4 0x5A /* Configuration Register 4 */
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| 200 | /* 0x5B */ /* Reserved */
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| 201 | #define RL_REVID 0x5E /* PCI Revision ID */
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| 202 | /* 0x5F */ /* Reserved */
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| 203 | #define RL_TSAD 0x60 /* Transmit Status of All Descriptors */
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| 204 | #define RL_TSAD_TOK3 0x8000 /* TOK bit of Descriptor 3 */
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| 205 | #define RL_TSAD_TOK2 0x4000 /* TOK bit of Descriptor 2 */
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| 206 | #define RL_TSAD_TOK1 0x2000 /* TOK bit of Descriptor 1 */
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| 207 | #define RL_TSAD_TOK0 0x1000 /* TOK bit of Descriptor 0 */
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| 208 | #define RL_TSAD_TUN3 0x0800 /* TUN bit of Descriptor 3 */
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| 209 | #define RL_TSAD_TUN2 0x0400 /* TUN bit of Descriptor 2 */
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| 210 | #define RL_TSAD_TUN1 0x0200 /* TUN bit of Descriptor 1 */
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| 211 | #define RL_TSAD_TUN0 0x0100 /* TUN bit of Descriptor 0 */
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| 212 | #define RL_TSAD_TABT3 0x0080 /* TABT bit of Descriptor 3 */
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| 213 | #define RL_TSAD_TABT2 0x0040 /* TABT bit of Descriptor 2 */
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| 214 | #define RL_TSAD_TABT1 0x0020 /* TABT bit of Descriptor 1 */
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| 215 | #define RL_TSAD_TABT0 0x0010 /* TABT bit of Descriptor 0 */
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| 216 | #define RL_TSAD_OWN3 0x0008 /* OWN bit of Descriptor 3 */
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| 217 | #define RL_TSAD_OWN2 0x0004 /* OWN bit of Descriptor 2 */
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| 218 | #define RL_TSAD_OWN1 0x0002 /* OWN bit of Descriptor 1 */
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| 219 | #define RL_TSAD_OWN0 0x0001 /* OWN bit of Descriptor 0 */
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| 220 | #define RL_BMCR 0x62 /* Basic Mode Control Register (MII_CTRL) */
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| 221 | #define RL_BMSR 0x64 /* Basic Mode Status Register (MII_STATUS) */
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| 222 | #define RL_ANAR 0x66 /* Auto-Neg Advertisement Register (MII_ANA) */
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| 223 | #define RL_ANLPAR 0x68 /* Auto-Neg Link Partner Register (MII_ANLPA) */
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| 224 | #define RL_ANER 0x6a /* Auto-Neg Expansion Register (MII_ANE) */
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| 225 | #define RL_NWAYTR 0x70 /* N-way Test Register */
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| 226 | #define RL_CSCR 0x74 /* CS Configuration Register */
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| 227 | #define RL_CONFIG5 0xD8 /* Configuration Register 5 */
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| 228 |
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| 229 | /* Status word in receive buffer */
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| 230 | #define RL_RXS_LEN_M 0xFFFF0000 /* Length Field, Excl. Status word */
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| 231 | #define RL_RXS_LEN_S 16 /* Shift For Length */
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| 232 | #define RL_RXS_MAR 0x00008000 /* Multicast Address Received */
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| 233 | #define RL_RXS_PAR 0x00004000 /* Physical Address Matched */
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| 234 | #define RL_RXS_BAR 0x00002000 /* Broadcast Address Received */
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| 235 | #define RL_RXS_RES_M 0x00001FC0 /* Reserved */
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| 236 | #define RL_RXS_ISE 0x00000020 /* Invalid Symbol Error */
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| 237 | #define RL_RXS_RUNT 0x00000010 /* Runt Packet Received */
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| 238 | #define RL_RXS_LONG 0x00000008 /* Long (>4KB) Packet */
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| 239 | #define RL_RXS_CRC 0x00000004 /* CRC Error */
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| 240 | #define RL_RXS_FAE 0x00000002 /* Frame Alignment Error */
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| 241 | #define RL_RXS_ROK 0x00000001 /* Receive OK */
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| 242 |
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| 243 | /* Registers in the Machine Independent Interface (MII) to the PHY.
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| 244 | * IEEE 802.3 (2000 Edition) Clause 22.
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| 245 | */
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| 246 | #define MII_CTRL 0x0 /* Control Register (basic) */
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| 247 | #define MII_CTRL_RST 0x8000 /* Reset PHY */
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| 248 | #define MII_CTRL_LB 0x4000 /* Enable Loopback Mode */
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| 249 | #define MII_CTRL_SP_LSB 0x2000 /* Speed Selection (LSB) */
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| 250 | #define MII_CTRL_ANE 0x1000 /* Auto Negotiation Enable */
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| 251 | #define MII_CTRL_PD 0x0800 /* Power Down */
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| 252 | #define MII_CTRL_ISO 0x0400 /* Isolate */
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| 253 | #define MII_CTRL_RAN 0x0200 /* Restart Auto-Negotiation Process */
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| 254 | #define MII_CTRL_DM 0x0100 /* Full Duplex */
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| 255 | #define MII_CTRL_CT 0x0080 /* Enable COL Signal Test */
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| 256 | #define MII_CTRL_SP_MSB 0x0040 /* Speed Selection (MSB) */
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| 257 | #define MII_CTRL_SP_10 0x0000 /* 10 Mb/s */
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| 258 | #define MII_CTRL_SP_100 0x2000 /* 100 Mb/s */
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| 259 | #define MII_CTRL_SP_1000 0x0040 /* 1000 Mb/s */
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| 260 | #define MII_CTRL_SP_RES 0x2040 /* Reserved */
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| 261 | #define MII_CTRL_RES 0x003F /* Reserved */
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| 262 | #define MII_STATUS 0x1 /* Status Register (basic) */
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| 263 | #define MII_STATUS_100T4 0x8000 /* 100Base-T4 support */
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| 264 | #define MII_STATUS_100XFD 0x4000 /* 100Base-X FD support */
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| 265 | #define MII_STATUS_100XHD 0x2000 /* 100Base-X HD support */
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| 266 | #define MII_STATUS_10FD 0x1000 /* 10 Mb/s FD support */
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| 267 | #define MII_STATUS_10HD 0x0800 /* 10 Mb/s HD support */
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| 268 | #define MII_STATUS_100T2FD 0x0400 /* 100Base-T2 FD support */
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| 269 | #define MII_STATUS_100T2HD 0x0200 /* 100Base-T2 HD support */
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| 270 | #define MII_STATUS_EXT_STAT 0x0100 /* Supports MII_EXT_STATUS */
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| 271 | #define MII_STATUS_RES 0x0080 /* Reserved */
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| 272 | #define MII_STATUS_MFPS 0x0040 /* MF Preamble Suppression */
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| 273 | #define MII_STATUS_ANC 0x0020 /* Auto-Negotiation Completed */
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| 274 | #define MII_STATUS_RF 0x0010 /* Remote Fault Detected */
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| 275 | #define MII_STATUS_ANA 0x0008 /* Auto-Negotiation Ability */
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| 276 | #define MII_STATUS_LS 0x0004 /* Link Up */
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| 277 | #define MII_STATUS_JD 0x0002 /* Jabber Condition Detected */
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| 278 | #define MII_STATUS_EC 0x0001 /* Ext Register Capabilities */
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| 279 | #define MII_PHYID_H 0x2 /* PHY ID (high) */
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| 280 | #define MII_PHYID_L 0x3 /* PHY ID (low) */
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| 281 | #define MII_ANA 0x4 /* Auto-Negotiation Advertisement */
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| 282 | #define MII_ANA_NP 0x8000 /* Next PAge */
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| 283 | #define MII_ANA_RES 0x4000 /* Reserved */
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| 284 | #define MII_ANA_RF 0x2000 /* Remote Fault */
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| 285 | #define MII_ANA_TAF_M 0x1FE0 /* Technology Ability Field */
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| 286 | #define MII_ANA_TAF_S 5 /* Shift */
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| 287 | #define MII_ANA_TAF_RES 0x1000 /* Reserved */
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| 288 | #define MII_ANA_PAUSE_ASYM 0x0800 /* Asym. Pause */
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| 289 | #define MII_ANA_PAUSE_SYM 0x0400 /* Sym. Pause */
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| 290 | #define MII_ANA_100T4 0x0200 /* 100Base-T4 */
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| 291 | #define MII_ANA_100TXFD 0x0100 /* 100Base-TX FD */
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| 292 | #define MII_ANA_100TXHD 0x0080 /* 100Base-TX HD */
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| 293 | #define MII_ANA_10TFD 0x0040 /* 10Base-T FD */
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| 294 | #define MII_ANA_10THD 0x0020 /* 10Base-T HD */
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| 295 | #define MII_ANA_SEL_M 0x001F /* Selector Field */
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| 296 | #define MII_ANA_SEL_802_3 0x0001 /* 802.3 */
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| 297 | #define MII_ANLPA 0x5 /* Auto-Neg Link Partner Ability Register */
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| 298 | #define MII_ANLPA_NP 0x8000 /* Next Page */
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| 299 | #define MII_ANLPA_ACK 0x4000 /* Acknowledge */
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| 300 | #define MII_ANLPA_RF 0x2000 /* Remote Fault */
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| 301 | #define MII_ANLPA_TAF_M 0x1FC0 /* Technology Ability Field */
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| 302 | #define MII_ANLPA_SEL_M 0x001F /* Selector Field */
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| 303 | #define MII_ANE 0x6 /* Auto-Negotiation Expansion */
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| 304 | #define MII_ANE_RES 0xFFE0 /* Reserved */
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| 305 | #define MII_ANE_PDF 0x0010 /* Parallel Detection Fault */
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| 306 | #define MII_ANE_LPNPA 0x0008 /* Link Partner is Next Page Able */
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| 307 | #define MII_ANE_NPA 0x0002 /* Local Device is Next Page Able */
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| 308 | #define MII_ANE_PR 0x0002 /* New Page has been received */
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| 309 | #define MII_ANE_LPANA 0x0001 /* Link Partner is Auto-Neg.able */
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| 310 | #define MII_ANNPT 0x7 /* Auto-Negotiation Next Page Transmit */
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| 311 | #define MII_ANLPRNP 0x8 /* Auto-Neg Link Partner Received Next Page */
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| 312 | #define MII_MS_CTRL 0x9 /* MASTER-SLAVE Control Register */
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| 313 | #define MII_MS_STATUS 0xA /* MASTER-SLAVE Status Register */
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| 314 | /* 0xB ... 0xE */ /* Reserved */
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| 315 | #define MII_EXT_STATUS 0xF /* Extended Status */
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| 316 | #define MII_ESTAT_1000XFD 0x8000 /* 1000Base-X Full Duplex */
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| 317 | #define MII_ESTAT_1000XHD 0x4000 /* 1000Base-X Half Duplex */
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| 318 | #define MII_ESTAT_1000TFD 0x2000 /* 1000Base-T Full Duplex */
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| 319 | #define MII_ESTAT_1000THD 0x1000 /* 1000Base-T Half Duplex */
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| 320 | #define MII_ESTAT_RES 0x0FFF /* Reserved */
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| 321 | /* 0x10 ... 0x1F */ /* Vendor Specific */
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| 322 |
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| 323 | #if 0
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| 324 | 34-35 R ERBCR Early Receive (Rx) Byte Count Register
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| 325 | 36 R ERSR Early Rx Status Register
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| 326 | 7-4 reserved
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| 327 | 3 R ERGood Early Rx Good packet
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| 328 | 2 R ERBad Early Rx Bad packet
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| 329 | 1 R EROVW Early Rx OverWrite
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| 330 | 0 R EROK Early Rx OK
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| 331 | 51 R/W CONFIG0 Configuration Register 0
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| 332 | 7 R SCR Scrambler Mode
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| 333 | 6 R PCS PCS Mode
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| 334 | 5 R T10 10 Mbps Mode
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| 335 | 4-3 R PL[1-0] Select 10 Mbps medium type
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| 336 | 2-0 R BS[2-0] Select Boot ROM size
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| 337 | 52 R/W CONFIG1 Configuration Register 1
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| 338 | 7-6 R/W LEDS[1-0] LED PIN
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| 339 | 5 R/W DVRLOAD Driver Load
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| 340 | 4 R/W LWACT LWAKE active mode
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| 341 | 3 R MEMMAP Memory Mapping
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| 342 | 2 R IOMAP I/O Mapping
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| 343 | 1 R/W VPD Set to enable Vital Product Data
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| 344 | 0 R/W PMEn Power Management Enable
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| 345 | 59 R/W CONFIG3 Configuration Register 3
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| 346 | 7 R GNTSel Gnt Select
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| 347 | 6 R/W PARM_En Parameter Enable
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| 348 | 5 R/W Magic Magic Packet
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| 349 | 4 R/W LinkUp Link Up
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| 350 | 3 reserved
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| 351 | 2 R CLKRUN_En CLKRUN Enable
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| 352 | 1 reserved
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| 353 | 0 R FBtBEn Fast Back to Back Enable
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| 354 | 5a R/W CONFIG4 Configuration Register 4
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| 355 | 7 R/W RxFIFOAutoClr Auto Clear the Rx FIFO on overflow
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| 356 | 6 R/W AnaOff Analog Power Off
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| 357 | 5 R/W LongWF Long Wake-up Frame
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| 358 | 4 R/W LWPME LANWAKE vs PMEB
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| 359 | 3 reserved
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| 360 | 2 R/W LWPTN LWAKE pattern
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| 361 | 1 reserved
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| 362 | 0 R/W PBWakeup Pre-Boot Wakeup
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| 363 | 5c-5d R/W MULINT Multiple Interrupt Select
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| 364 | 15-12 reserved
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| 365 | 11-0 R/W MISR[11-0] Multiple Interrupt Select
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| 366 | 68-69 R ANLPAR Auto-Negotiation Link Partnet Register
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| 367 | 15 R NP Next Page bit
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| 368 | 14 R ACK acknowledge received from link partner
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| 369 | 13 R/W RF received remote fault detection capability
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| 370 | 12-11 reserved
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| 371 | 10 R Pause Flow control is supported
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| 372 | 9 R T4 100Base-T4 is supported
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| 373 | 8 R/W TXFD 100Base-TX full duplex is supported
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| 374 | 7 R/W TX 100Base-TX is supported
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| 375 | 6 R/W 10FD 10Base-T full duplex is supported
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| 376 | 5 R/W 10 10Base-T is supported
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| 377 | 4-0 R/W Selector Binary encoded selector
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| 378 | 6a-6b R ANER Auto-Negotiation Expansion Register
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| 379 | 15-5 reserved
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| 380 | 4 R MLF Multiple link fault occured
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| 381 | 3 R LP_NP_ABLE Link partner supports Next Page
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| 382 | 2 R NP_ABLE Local node is able to send add. Next Pages
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| 383 | 1 R PAGE_RX Link Code Word Page received
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| 384 | 0 R LP_NW_ABLE Link partner supports NWay auto-negotiation
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| 385 | 70-71 R/W NWAYTR N-way Test Register
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| 386 | 15-8 reserved
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| 387 | 7 R/W NWLPBK NWay loopback mode
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| 388 | 6-4 reserved
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| 389 | 3 R ENNWLE LED0 pin indicates linkpulse
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| 390 | 2 R FLAGABD Auto-neg experienced ability detect state
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| 391 | 1 R FLAGPDF Auto-neg exp. par. detection fault state
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| 392 | 0 R FLAGLSC Auto-neg experienced link status check state
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| 393 | 74-75 R/W CSCR CS Configuration Register
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| 394 | 15 W Testfun Auto-neg speeds up internal timer
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| 395 | 14-10 reserved
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| 396 | 9 R/W LD Active low TPI link disable signal
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| 397 | 8 R/W HEARTBEAT HEART BEAT enable
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| 398 | 7 R/W JBEN Enable jabber function
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| 399 | 6 R/W F_LINK_100 Force 100 Mbps
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| 400 | 5 R/W F_Conect Bypass disconnect function
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| 401 | 4 reserved
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| 402 | 3 R Con_status Connected link detected
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| 403 | 2 R/W Con_status_En Configures LED1 to indicate conn. stat.
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| 404 | 1 reserved
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| 405 | 0 R/W PASS_SCR Bypass scramble
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| 406 | 76-77 reserved
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| 407 | 78-7b R/W PHY1_PARM PHY parameter 1
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| 408 | 7c-7f R/W TW_PARM Twister parameter
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| 409 | 80 R/W PHY2_PARM PHY parameter 2
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| 410 | 81-83 reserved
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| 411 | 84-8b R/W CRC[0-7] Power Management CRC reg.[0-7] for frame[0-7]
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| 412 | 8c-cb R/W Wakeup[0-7] Power Management wakeup frame[0-7] (64 bit)
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| 413 | cc-d3 R/W LSBCRC[0-7] LSB of the mask byte of makeup frame[0-7]
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| 414 | d4-d7 reserved
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| 415 | d8 R/W Config5 Configuration register 5
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| 416 | 7 reserved
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| 417 | 6 R/W BWF Broadcast Wakeup Frame
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| 418 | 5 R/W MWF Multicast Wakeup Frame
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| 419 | 4 R/W UWF Unicast Wakeup Frame
|
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| 420 | 3 R/W FifoAddrPtr FIFO Address Pointer
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| 421 | 2 R/W LDPS Link Down Power Saving mode
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| 422 | 1 R/W LANWake LANWake Signal
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| 423 | 0 R/W PME_STS PME_Status bit
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| 424 | d9-ff reserved
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| 425 | #endif
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| 426 |
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| 427 | /*
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| 428 | * $PchId: rtl8139.h,v 1.1 2003/09/05 10:58:50 philip Exp $
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| 429 | */
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