| 1 | /*
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| 2 | i82365.h
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| 3 |
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| 4 | Created: May 1995 by Philip Homburg <philip@cs.vu.nl>
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| 5 | */
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| 6 |
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| 7 | #ifndef I82365_H
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| 8 | #define I82365_H
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| 9 |
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| 10 | /* The default I/O ports used by a i82365 are the following: */
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| 11 | #define I365_INDEX 0x3E0
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| 12 | #define I365_DATA 0x3E1
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| 13 |
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| 14 | /* The index register is used to select one of the following registers: */
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| 15 | #define I365_REVISION 0x00 /* IDREG */
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| 16 | #define I365R_ID_MASK 0xC0
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| 17 | #define I365R_ID_IO 0x00
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| 18 | #define I365R_ID_MEM 0x40
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| 19 | #define I365R_ID_MEM_IO 0x80
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| 20 | #define I365R_RES_MASK 0x30
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| 21 | #define I365R_REV_MASK 0x0F
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| 22 |
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| 23 | #define I365_IF_STAT 0x01 /* ISTAT */
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| 24 | #define I365IS_GPI 0x80
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| 25 | #define CL6722IS_VPPVALID 0x80
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| 26 | #define I365IS_POWER 0x40
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| 27 | #define I365IS_READY 0x20
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| 28 | #define I365IS_WRTPROT 0x10
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| 29 | #define I365IS_CARD_MASK 0x0C
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| 30 | #define I365IS_CARD_ABSENT 0x00
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| 31 | #define I365IS_CARD_PART_0 0x04
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| 32 | #define I365IS_CARD_PART_1 0x08
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| 33 | #define I365IS_CARD_PRESENT 0x0C
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| 34 | #define I365IS_BAT_MASK 0x03
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| 35 | #define I365IS_BAT_LOST_0 0x00
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| 36 | #define I365IS_BAT_LOW 0x01
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| 37 | #define I365IS_BAT_LOST_1 0x02
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| 38 | #define I365IS_BAT_OKAY 0x03
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| 39 |
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| 40 | #define I365_PWR_CTL 0x02 /* PCTRL */
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| 41 | #define I365PC_CARD_EN 0x80
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| 42 | #define I365PC_NORESET 0x40
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| 43 | #define CL6722PC_COMPAT_0 0x40
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| 44 | #define I365PC_AUTO_PWR 0x20
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| 45 | #define I365PC_Vcc_MASK 0x18
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| 46 | #define I365PC_Vcc_NC 0x00
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| 47 | #define I365PC_Vcc_Reserved 0x08
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| 48 | #define I365PC_Vcc_5 0x10
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| 49 | #define I365PC_Vcc_33 0x18
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| 50 | #define CL6722PC_Vcc_PWR 0x10
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| 51 | #define CL6722PC_COMPAT_1 0x08
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| 52 | #define I365PC_Vpp_MASK 0x03
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| 53 | #define I365PC_Vpp_NC 0x00
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| 54 | #define CL6722PC_Vpp_ZERO_0 0x00
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| 55 | #define I365PC_Vpp_5 0x01
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| 56 | #define CL6722PC_Vpp_Vcc 0x01
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| 57 | #define I365PC_Vpp_12 0x02
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| 58 | #define I365PC_Vpp_Reserved 0x03
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| 59 | #define CL6722PC_Vpp_ZERO_1 0x03
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| 60 |
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| 61 | #define I365_INT_GEN_CTL 0x03
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| 62 | #define I365IGC_RING_IND 0x80
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| 63 | #define I365IGC_RESET 0x40
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| 64 | #define I365IGC_CARD_IS_IO 0x20
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| 65 | #define I365IGC_EN_MNG_INT 0x10
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| 66 | #define I365IGC_IRQ_MASK 0x0F
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| 67 |
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| 68 | #define I365_CRD_STAT_CHG 0x04 /* CSTCH */
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| 69 | #define I365CSC_GPI 0x10
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| 70 | #define I365CSC_CARD_DETECT 0x08
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| 71 | #define I365CSC_READY 0x04
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| 72 | #define I365CSC_BAT_WARN 0x02
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| 73 | #define I365CSC_BAT_DEAD 0x01
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| 74 |
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| 75 | #define I365_MNG_INT_CONF 0x05
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| 76 | #define I365MIC_IRQ_MASK 0xF0
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| 77 | #define I365MIC_CARD_DETECT 0x08
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| 78 | #define I365MIC_READY 0x04
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| 79 | #define I365MIC_BAT_WARN 0x02
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| 80 | #define I365MIC_BAT_DEAD 0x01
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| 81 |
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| 82 | #define I365_MAP_ENABLE 0x06 /* ADWEN */
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| 83 | #define I365ME_IO_MAP_0 0x40
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| 84 | #define I365ME_MEM_MAP_0 0x01
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| 85 |
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| 86 | #define I365_IO_WND_CTL 0x07
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| 87 | #define I365IWC_AUTO_1 0x80
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| 88 | #define CL6722IWC_TIMING_1 0x80
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| 89 | #define I365IWC_0WS_1 0x40
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| 90 | #define I365IWC_AUTO_SIZE_1 0x20
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| 91 | #define I365IWC_IO_SIZE_1 0x10
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| 92 | #define I365IWC_WAIT_0 0x08
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| 93 | #define I365IWC_0WS_0 0x04
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| 94 | #define CL6722IWC_TIMING_0 0x08
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| 95 | #define I365IWC_AUTO_SIZE_0 0x02
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| 96 | #define I365IWC_IO_SIZE_0 0x01
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| 97 |
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| 98 | #define I365_IO_0_START_LOW 0x08
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| 99 | #define I365_IO_0_START_HIGH 0x09
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| 100 | #define I365_IO_0_END_LOW 0x0A
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| 101 | #define I365_IO_0_END_HIGH 0x0B
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| 102 | #define I365_IO_1_START_LOW 0x0C
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| 103 | #define I365_IO_1_START_HIGH 0x0D
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| 104 | #define I365_IO_1_END_LOW 0x0E
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| 105 | #define I365_IO_1_END_HIGH 0x0F
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| 106 |
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| 107 | #define I365_MEM_0_START_LOW 0x10
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| 108 | #define I365_MEM_0_START_HIGH 0x11
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| 109 | #define I365_MEM_0_END_LOW 0x12
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| 110 | #define I365_MEM_0_END_HIGH 0x13
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| 111 | #define I365_MEM_0_OFF_LOW 0x14
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| 112 | #define I365_MEM_0_OFF_HIGH 0x15
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| 113 |
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| 114 | #define CL6722_MISC_CTL_1 0x16
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| 115 | #define CL6722_FIFO_CTL 0x17
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| 116 |
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| 117 | #define I365_MEM_1_START_LOW 0x18
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| 118 | #define I365_MEM_1_START_HIGH 0x19
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| 119 | #define I365_MEM_1_END_LOW 0x1A
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| 120 | #define I365_MEM_1_END_HIGH 0x1B
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| 121 | #define I365_MEM_1_OFF_LOW 0x1C
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| 122 | #define I365_MEM_1_OFF_HIGH 0x1D
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| 123 |
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| 124 | #define CL6722_MISC_CTL_2 0x1E
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| 125 | #define CL6722_CHIP_INFO 0x1F
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| 126 | #define CL6722CI_ID_MASK 0xC0
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| 127 |
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| 128 | #define I365_MEM_2_START_LOW 0x20
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| 129 | #define I365_MEM_2_START_HIGH 0x21
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| 130 | #define I365_MEM_2_END_LOW 0x22
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| 131 | #define I365_MEM_2_END_HIGH 0x23
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| 132 | #define I365_MEM_2_OFF_LOW 0x24
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| 133 | #define I365_MEM_2_OFF_HIGH 0x25
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| 134 |
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| 135 | #define CL6722_ATA_CONTROL 0x26 /* CPAGE */
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| 136 | #define I365_RESERVED 0x27
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| 137 |
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| 138 | #define I365_MEM_3_START_LOW 0x28
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| 139 | #define I365_MEM_3_START_HIGH 0x29
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| 140 | #define I365_MEM_3_END_LOW 0x2A
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| 141 | #define I365_MEM_3_END_HIGH 0x2B
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| 142 | #define I365_MEM_3_OFF_LOW 0x2C
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| 143 | #define I365_MEM_3_OFF_HIGH 0x2D
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| 144 |
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| 145 | #define CL6722_EXT_INDEX 0x2E /* CSCTRL */
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| 146 | #define CL6722_EXT_DATA 0x2F
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| 147 |
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| 148 | #define I365_MEM_4_START_LOW 0x30
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| 149 | #define I365_MEM_4_START_HIGH 0x31
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| 150 | #define I365_MEM_4_END_LOW 0x32
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| 151 | #define I365_MEM_4_END_HIGH 0x33
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| 152 | #define I365_MEM_4_OFF_LOW 0x34
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| 153 | #define I365_MEM_4_OFF_HIGH 0x35
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| 154 |
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| 155 | #define CL6722_IO_0_OFF_LOW 0x36
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| 156 | #define CL6722_IO_0_OFF_HIGH 0x37
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| 157 | #define CL6722_IO_1_OFF_LOW 0x38
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| 158 | #define CL6722_IO_1_OFF_HIGH 0x39
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| 159 |
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| 160 | #define I365_SETUP_TIM_0 0x3A
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| 161 | #define I365_CMD_TIM_0 0x3B
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| 162 | #define I365_RECOV_TIM_0 0x3C
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| 163 | #define I365_SETUP_TIM_1 0x3D
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| 164 | #define I365_CMD_TIM_1 0x3E
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| 165 | #define I365_RECOV_TIM_1 0x3F
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| 166 |
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| 167 | #endif /* I82365_H */
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