source: trunk/minix/include/ibm/pci.h@ 9

Last change on this file since 9 was 9, checked in by Mattia Monga, 14 years ago

Minix 3.1.2a
File size: 5.6 KB
Line 
1/*
2pci.h
3
4Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
5*/
6
7/* Header type 00, normal PCI devices */
8#define PCI_VID 0x00 /* Vendor ID, 16-bit */
9#define PCI_DID 0x02 /* Device ID, 16-bit */
10#define PCI_CR 0x04 /* Command Register, 16-bit */
11#define PCI_CR_MAST_EN 0x0004 /* Enable Busmaster Access */
12#define PCI_CR_IO_EN 0x0001 /* Enable I/O Cycles */
13#define PCI_SR 0x06 /* PCI status, 16-bit */
14#define PSR_SSE 0x4000 /* Signaled System Error */
15#define PSR_RMAS 0x2000 /* Received Master Abort Status */
16#define PSR_RTAS 0x1000 /* Received Target Abort Status */
17#define PSR_CAPPTR 0x0010 /* Capabilities list */
18#define PCI_REV 0x08 /* Revision ID */
19#define PCI_PIFR 0x09 /* Prog. Interface Register */
20#define PCI_SCR 0x0A /* Sub-Class Register */
21#define PCI_BCR 0x0B /* Base-Class Register */
22#define PCI_CLS 0x0C /* Cache Line Size */
23#define PCI_LT 0x0D /* Latency Timer */
24#define PCI_HEADT 0x0E /* Header type, 8-bit */
25#define PHT_MASK 0x7F /* Header type mask */
26#define PHT_NORMAL 0x00
27#define PHT_BRIDGE 0x01
28#define PHT_CARDBUS 0x02
29#define PHT_MULTIFUNC 0x80 /* Multiple functions */
30#define PCI_BIST 0x0F /* Built-in Self Test */
31#define PCI_BAR 0x10 /* Base Address Register */
32#define PCI_BAR_IO 0x00000001 /* Reg. refers to I/O space */
33#define PCI_BAR_TYPE 0x00000006 /* Memory BAR type */
34#define PCI_BAR_PREFETCH 0x00000008 /* Memory is prefetchable */
35#define PCI_BAR_2 0x14 /* Base Address Register */
36#define PCI_BAR_3 0x18 /* Base Address Register */
37#define PCI_BAR_4 0x1C /* Base Address Register */
38#define PCI_BAR_5 0x20 /* Base Address Register */
39#define PCI_BAR_6 0x24 /* Base Address Register */
40#define PCI_CBCISPTR 0x28 /* Cardbus CIS Pointer */
41#define PCI_SUBVID 0x2C /* Subsystem Vendor ID */
42#define PCI_SUBDID 0x2E /* Subsystem Device ID */
43#define PCI_EXPROM 0x30 /* Expansion ROM Base Address */
44#define PCI_CAPPTR 0x34 /* Capabilities Pointer */
45#define PCI_CP_MASK 0xfc /* Lower 2 bits should be ignored */
46#define PCI_ILR 0x3C /* Interrupt Line Register */
47#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */
48#define PCI_IPR 0x3D /* Interrupt Pin Register */
49#define PCI_MINGNT 0x3E /* Min Grant */
50#define PCI_MAXLAT 0x3F /* Max Latency */
51
52/* Header type 01, PCI-to-PCI bridge devices */
53/* The following registers are in common with type 00:
54 * PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR,
55 * PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_BAR2, PCI_CAPPTR,
56 * PCI_ILR, PCI_IPR.
57 */
58#define PPB_PRIMBN 0x18 /* Primary Bus Number */
59#define PPB_SECBN 0x19 /* Secondary Bus Number */
60#define PPB_SUBORDBN 0x1A /* Subordinate Bus Number */
61#define PPB_SECBLT 0x1B /* Secondary Bus Latency Timer */
62#define PPB_IOBASE 0x1C /* I/O Base */
63#define PPB_IOB_MASK 0xf0
64#define PPB_IOLIMIT 0x1D /* I/O Limit */
65#define PPB_IOL_MASK 0xf0
66#define PPB_SSTS 0x1E /* Secondary Status Register */
67#define PPB_MEMBASE 0x20 /* Memory Base */
68#define PPB_MEMB_MASK 0xfff0
69#define PPB_MEMLIMIT 0x22 /* Memory Limit */
70#define PPB_MEML_MASK 0xfff0
71#define PPB_PFMEMBASE 0x24 /* Prefetchable Memory Base */
72#define PPB_PFMEMB_MASK 0xfff0
73#define PPB_PFMEMLIMIT 0x26 /* Prefetchable Memory Limit */
74#define PPB_PFMEML_MASK 0xfff0
75#define PPB_PFMBU32 0x28 /* Prefetchable Memory Base Upper 32 */
76#define PPB_PFMLU32 0x2C /* Prefetchable Memory Limit Upper 32 */
77#define PPB_IOBASEU16 0x30 /* I/O Base Upper 16 */
78#define PPB_IOLIMITU16 0x32 /* I/O Limit Upper 16 */
79#define PPB_EXPROM 0x38 /* Expansion ROM Base Address */
80#define PPB_BRIDGECTRL 0x3E /* Bridge Control */
81#define PPB_BC_CRST 0x40 /* Assert reset line */
82
83/* Header type 02, Cardbus bridge devices */
84/* The following registers are in common with type 00:
85 * PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR,
86 * PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_ILR, PCI_IPR.
87 */
88/* The following registers are in common with type 01:
89 * PPB_PRIMBN, PPB_SECBN, PPB_SUBORDBN, PPB_SECBLT.
90 */
91#define CBB_CAPPTR 0x14 /* Capability Pointer */
92#define CBB_SSTS 0x16 /* Secondary Status Register */
93#define CBB_MEMBASE_0 0x1C /* Memory Base 0 */
94#define CBB_MEMLIMIT_0 0x20 /* Memory Limit 0 */
95#define CBB_MEML_MASK 0xfffff000
96#define CBB_MEMBASE_1 0x24 /* Memory Base 1 */
97#define CBB_MEMLIMIT_1 0x28 /* Memory Limit 1 */
98#define CBB_IOBASE_0 0x2C /* I/O Base 0 */
99#define CBB_IOLIMIT_0 0x30 /* I/O Limit 0 */
100#define CBB_IOL_MASK 0xfffffffc
101#define CBB_IOBASE_1 0x34 /* I/O Base 1 */
102#define CBB_IOLIMIT_1 0x38 /* I/O Limit 1 */
103#define CBB_BRIDGECTRL 0x3E /* Bridge Control */
104#define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */
105#define CBB_BC_CRST 0x40 /* Assert reset line */
106
107#define CAP_TYPE 0x00 /* Type field in capability */
108#define CAP_NEXT 0x01 /* Next field in capability */
109
110#define PCI_BCR_MASS_STORAGE 0x01 /* Mass Storage class */
111#define PCI_MS_IDE 0x01 /* IDE storage class */
112#define PCI_IDE_PRI_NATIVE 0x01 /* Primary channel is
113 * in native mode.
114 */
115#define PCI_IDE_SEC_NATIVE 0x04 /* Secondary channel is
116 * in native mode.
117 */
118
119/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */
120#define PCI_T3_VGA_OLD 0x000100 /* OLD VGA class code */
121#define PCI_T3_RAID 0x010400 /* RAID controller */
122#define PCI_T3_VGA 0x030000 /* VGA-compatible video card */
123#define PCI_T3_ISA 0x060100 /* ISA bridge */
124#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */
125#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */
126#define PCI_T3_CARDBUS 0x060700 /* Bardbus Bridge */
127
128#define NO_VID 0xffff /* No PCI card present */
129
130/*
131 * $PchId: pci.h,v 1.4 2001/12/06 20:21:22 philip Exp $
132 */
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