Index: trunk/minix/include/ibm/bios.h =================================================================== --- trunk/minix/include/ibm/bios.h (revision 9) +++ (revision ) @@ -1,125 +1,0 @@ -/* Definitions of several known BIOS addresses. The addresses listed here - * are found in three memory areas that have been defined in . - * - the BIOS interrupt vectors - * - the BIOS data area - * - the motherboard BIOS memory - * - * Created: March 2005, Jorrit N. Herder - */ - -#ifndef _BIOS_H -#define _BIOS_H - -/* PART I -- - * The BIOS interrupt vector table (IVT) area (1024 B as of address 0x0000). - * Although this area holds 256 interrupt vectors (with jump addresses), some - * vectors actually contain important BIOS data. Some addresses are below. - */ -#define BIOS_EQUIP_CHECK_ADDR 0x0044 -#define BIOS_EQUIP_CHECK_SIZE 4L - -#define BIOS_VIDEO_PARAMS_ADDR 0x0074 -#define BIOS_VIDEO_PARAMS_SIZE 4L - -#define BIOS_FLOP_PARAMS_ADDR 0x0078 -#define BIOS_FLOP_PARAMS_SIZE 4L - -#define BIOS_HD0_PARAMS_ADDR 0x0104 /* disk 0 parameters */ -#define BIOS_HD0_PARAMS_SIZE 4L - -#define BIOS_HD1_PARAMS_ADDR 0x0118 /* disk 1 parameters */ -#define BIOS_HD1_PARAMS_SIZE 4L - -/* PART I -- - * Addresses in the BIOS data area (256 B as of address 0x0400). The addresses - * listed below are the most important ones, and the ones that are currently - * used. Other addresses may be defined below when new features are added. - */ - -/* Serial ports (COM1-COM4). */ -#define COM1_IO_PORT_ADDR 0x400 /* COM1 port address */ -#define COM1_IO_PORT_SIZE 2L -#define COM2_IO_PORT_ADDR 0x402 /* COM2 port address */ -#define COM2_IO_PORT_SIZE 2L -#define COM3_IO_PORT_ADDR 0x404 /* COM3 port address */ -#define COM3_IO_PORT_SIZE 2L -#define COM4_IO_PORT_ADDR 0x406 /* COM4 port address */ -#define COM4_IO_PORT_SIZE 2L - -/* Parallel ports (LPT1-LPT4). */ -#define LPT1_IO_PORT_ADDR 0x408 /* LPT1 port address */ -#define LPT1_IO_PORT_SIZE 2L -#define LPT2_IO_PORT_ADDR 0x40A /* LPT2 port address */ -#define LPT2_IO_PORT_SIZE 2L -#define LPT3_IO_PORT_ADDR 0x40C /* LPT3 port address */ -#define LPT3_IO_PORT_SIZE 2L -#define LPT4_IO_PORT_ADDR 0x40E /* LPT4 port (except on PS/2) */ -#define LPT4_IO_PORT_SIZE 2L - -/* Video controller (VDU). */ -#define VDU_SCREEN_COLS_ADDR 0x44A /* VDU nr of screen columns */ -#define VDU_SCREEN_COLS_SIZE 2L - -/* Base I/O port address for active 6845 CRT controller. */ -#define VDU_CRT_BASE_ADDR 0x463 /* 3B4h = mono, 3D4h = color */ -#define VDU_CRT_BASE_SIZE 2L - -/* Soft reset flags to control shutdown. */ -#define SOFT_RESET_FLAG_ADDR 0x472 /* soft reset flag on Ctl-Alt-Del */ -#define SOFT_RESET_FLAG_SIZE 2L -#define STOP_MEM_CHECK 0x1234 /* bypass memory tests & CRT init */ -#define PRESERVE_MEMORY 0x4321 /* preserve memory */ -#define SYSTEM_SUSPEND 0x5678 /* system suspend */ -#define MANUFACTURER_TEST 0x9ABC /* manufacturer test */ -#define CONVERTIBLE_POST 0xABCD /* convertible POST loop */ - /* ... many other values are used during POST */ - -/* Hard disk parameters. (Also see BIOS interrupt vector table above.) */ -#define NR_HD_DRIVES_ADDR 0x475 /* number of hard disk drives */ -#define NR_HD_DRIVES_SIZE 1L - -/* Parallel ports (LPT1-LPT4) timeout values. */ -#define LPT1_TIMEOUT_ADDR 0x478 /* time-out value for LPT1 */ -#define LPT1_TIMEOUT_SIZE 1L -#define LPT2_TIMEOUT_ADDR 0x479 /* time-out value for LPT2 */ -#define LPT2_TIMEOUT_SIZE 1L -#define LPT3_TIMEOUT_ADDR 0x47A /* time-out value for LPT3 */ -#define LPT3_TIMEOUT_SIZE 1L -#define LPT4_TIMEOUT_ADDR 0x47B /* time-out for LPT4 (except PS/2) */ -#define LPT4_TIMEOUT_SIZE 1L - -/* Serial ports (COM1-COM4) timeout values. */ -#define COM1_TIMEOUT_ADDR 0x47C /* time-out value for COM1 */ -#define COM1_TIMEOUT_SIZE 1L -#define COM2_TIMEOUT_ADDR 0x47D /* time-out value for COM2 */ -#define COM2_TIMEOUT_SIZE 1L -#define COM3_TIMEOUT_ADDR 0x47E /* time-out value for COM3 */ -#define COM3_TIMEOUT_SIZE 1L -#define COM4_TIMEOUT_ADDR 0x47F /* time-out value for COM4 */ -#define COM4_TIMEOUT_SIZE 1L - -/* Video controller (VDU). */ -#define VDU_SCREEN_ROWS_ADDR 0x484 /* screen rows (less 1, EGA+)*/ -#define VDU_SCREEN_ROWS_SIZE 1L -#define VDU_FONTLINES_ADDR 0x485 /* point height of char matrix */ -#define VDU_FONTLINES_SIZE 2L - -/* Video controller (VDU). */ -#define VDU_VIDEO_MODE_ADDR 0x49A /* current video mode */ -#define VDU_VIDEO_MODE_SIZE 1L - -/* PART III -- - * The motherboard BIOS memory contains some known values that are currently - * in use. Other sections in the upper memory area (UMA) addresses vary in - * size and locus and are not further defined here. A rough map is given in - * . - */ - -/* Machine ID (we're interested in PS/2 and AT models). */ -#define MACHINE_ID_ADDR 0xFFFFE /* BIOS machine ID byte */ -#define MACHINE_ID_SIZE 1L -#define PS_386_MACHINE 0xF8 /* ID byte for PS/2 modela 70/80 */ -#define PC_AT_MACHINE 0xFC /* PC/AT, PC/XT286, PS/2 models 50/60 */ - -#endif /* _BIOS_H */ - Index: trunk/minix/include/ibm/cmos.h =================================================================== --- trunk/minix/include/ibm/cmos.h (revision 9) +++ (revision ) @@ -1,85 +1,0 @@ -/* -ibm/cmos.h - -Created: Dec 1998 by Philip Homburg - -Definitions for the CMOS/realtime clock. Based on the datasheet for the -Dallas DS12887, compatible with the Motorola MC146818 -*/ - -#define RTC_INDEX 0x70 /* Bit 7 = NMI enable (1) / disable (0) - * bits 0..6 index - */ -#define RTC_IO 0x71 /* Data register, - * Note: the operation following a write to - * RTC_INDEX should an access (read or write) - * to RTC_IO - */ - -#define RTC_SEC 0x0 /* Seconds register */ -#define RTC_SEC_ALRM 0x1 /* Seconds register for alarm */ -#define RTC_MIN 0x2 /* Minutes register */ -#define RTC_MIN_ALRM 0x3 /* Minutes register for alarm */ -#define RTC_HOUR 0x4 /* Hours register */ -#define RTC_HOUR_ALRM 0x5 /* Hours register for alarm */ -#define RTC_WDAY 0x6 /* Day of the week, 1..7, Sunday = 1 */ -#define RTC_MDAY 0x7 /* Day of the month, 1..31 */ -#define RTC_MONTH 0x8 /* Month, 1..12 */ -#define RTC_YEAR 0x9 /* Year, 0..99 */ -#define RTC_REG_A 0xA -#define RTC_A_UIP 0x80 /* Update in progress. When clear, - * no update will occur for 244 - * micro seconds. - */ -#define RTC_A_DV 0x70 /* Divider bits, valid values are: */ -#define RTC_A_DV_OK 0x20 /* Normal */ -#define RTC_A_DV_STOP 0x70 /* Stop, a re-start starts - * halfway through a cycle, - * i.e. the update occurs after - * 500ms. - */ -#define RTC_A_RS 0x0F /* Int. freq */ - /* 0 None - * 1 256 Hz - * 2 128 Hz - * 3 8192 Hz - * 4 4096 Hz - * 5 2048 Hz - * 6 1024 Hz - * 7 512 Hz - * 8 256 Hz - * 9 128 Hz - * 10 64 Hz - * 11 32 Hz - * 12 16 Hz - * 13 8 Hz - * 14 4 Hz - * 15 2 Hz - */ -#define RTC_A_RS_DEF 6 /* Default freq. */ -#define RTC_REG_B 0xB -#define RTC_B_SET 0x80 /* Inhibit updates */ -#define RTC_B_PIE 0x40 /* Enable periodic interrupts */ -#define RTC_B_AIE 0x20 /* Enable alarm interrupts */ -#define RTC_B_UIE 0x10 /* Enable update ended interrupts */ -#define RTC_B_SQWE 0x08 /* Enable square wave output */ -#define RTC_B_DM_BCD 0x04 /* Data is in BCD (otherwise binary) */ -#define RTC_B_24 0x02 /* Count hours in 24-hour mode */ -#define RTC_B_DSE 0x01 /* Automatic (wrong) daylight savings - * updates - */ -#define RTC_REG_C 0xC - -/* Contents of the general purpose CMOS RAM (source IBM reference manual) */ -#define CMOS_STATUS 0xE -#define CS_LOST_POWER 0x80 /* Chip lost power */ -#define CS_BAD_CHKSUM 0x40 /* Checksum is incorrect */ -#define CS_BAD_CONFIG 0x20 /* Bad configuration info */ -#define CS_BAD_MEMSIZE 0x10 /* Wrong memory size of CMOS */ -#define CS_BAD_HD 0x08 /* Harddisk failed */ -#define CS_BAD_TIME 0x04 /* CMOS time is invalid */ - /* bits 0 and 1 are reserved */ - -/* - * $PchId: cmos.h,v 1.1 1998/12/16 09:14:21 philip Exp $ - */ Index: trunk/minix/include/ibm/cpu.h =================================================================== --- trunk/minix/include/ibm/cpu.h (revision 9) +++ (revision ) @@ -1,15 +1,0 @@ -#ifndef _IBM_CPU_H -#define _IBM_CPU_H 1 - -#define X86_FLAG_C (1L << 0) /* Carry */ -#define X86_FLAG_P (1L << 2) /* Parity */ -#define X86_FLAG_A (1L << 4) /* Aux. carry */ -#define X86_FLAG_Z (1L << 6) /* Zero */ -#define X86_FLAG_S (1L << 7) /* Sign */ - -#define X86_FLAG_T (1L << 8) /* Trap */ -#define X86_FLAG_I (1L << 9) /* Interrupt */ -#define X86_FLAG_D (1L << 10) /* Direction */ -#define X86_FLAG_O (1L << 11) /* Overflow */ - -#endif Index: trunk/minix/include/ibm/diskparm.h =================================================================== --- trunk/minix/include/ibm/diskparm.h (revision 9) +++ (revision ) @@ -1,20 +1,0 @@ -/* PC (and AT) BIOS structure to hold disk parameters. Under Minix, it is - * used mainly for formatting. - */ - -#ifndef _DISKPARM_H -#define _DISKPARM_H -struct disk_parameter_s { - char spec1; - char spec2; - char motor_turnoff_sec; - char sector_size_code; - char sectors_per_cylinder; - char gap_length; - char dtl; - char gap_length_for_format; - char fill_byte_for_format; - char head_settle_msec; - char motor_start_eigth_sec; -}; -#endif /* _DISKPARM_H */ Index: trunk/minix/include/ibm/int86.h =================================================================== --- trunk/minix/include/ibm/int86.h (revision 9) +++ (revision ) @@ -1,61 +1,0 @@ -/* int86.h - 8086 interrupt types Author: Kees J. Bot - * 3 May 2000 - */ - -/* Registers used in an PC real mode call for BIOS or DOS services. A - * driver is called through the vector if the interrupt number is zero. - */ -union reg86 { - struct l { - u32_t ef; /* 32 bit flags (output only) */ - u32_t vec; /* Driver vector (input only) */ - u32_t _ds_es[1]; - u32_t eax; /* 32 bit general registers */ - u32_t ebx; - u32_t ecx; - u32_t edx; - u32_t esi; - u32_t edi; - u32_t ebp; - } l; - struct w { - u16_t f, _ef[1]; /* 16 bit flags (output only) */ - u16_t off, seg; /* Driver vector (input only) */ - u16_t ds, es; /* DS and ES real mode segment regs */ - u16_t ax, _eax[1]; /* 16 bit general registers */ - u16_t bx, _ebx[1]; - u16_t cx, _ecx[1]; - u16_t dx, _edx[1]; - u16_t si, _esi[1]; - u16_t di, _edi[1]; - u16_t bp, _ebp[1]; - } w; - struct b { - u8_t intno, _intno[3]; /* Interrupt number (input only) */ - u8_t _vec[4]; - u8_t _ds_es[4]; - u8_t al, ah, _eax[2]; /* 8 bit general registers */ - u8_t bl, bh, _ebx[2]; - u8_t cl, ch, _ecx[2]; - u8_t dl, dh, _edx[2]; - u8_t _esi[4]; - u8_t _edi[4]; - u8_t _ebp[4]; - } b; -}; - -struct reg86u { union reg86 u; }; /* Better for forward declarations */ - -/* Parameters passed on ioctls to the memory task. */ - -struct mio_int86 { /* MIOCINT86 */ - union reg86 reg86; /* x86 registers as above */ - u16_t off, seg; /* Address of kernel buffer */ - void *buf; /* User data buffer */ - size_t len; /* Size of user buffer */ -}; - -struct mio_ldt86 { /* MIOCGLDT86, MIOCSLDT86 */ - size_t idx; /* Index in process' LDT */ - u16_t entry[4]; /* One LDT entry to get or set. */ -}; Index: trunk/minix/include/ibm/interrupt.h =================================================================== --- trunk/minix/include/ibm/interrupt.h (revision 9) +++ (revision ) @@ -1,61 +1,0 @@ -/* Interrupt numbers and hardware vectors. */ - -#ifndef _INTERRUPT_H -#define _INTERRUPT_H - -#if (CHIP == INTEL) - -/* 8259A interrupt controller ports. */ -#define INT_CTL 0x20 /* I/O port for interrupt controller */ -#define INT_CTLMASK 0x21 /* setting bits in this port disables ints */ -#define INT2_CTL 0xA0 /* I/O port for second interrupt controller */ -#define INT2_CTLMASK 0xA1 /* setting bits in this port disables ints */ - -/* Magic numbers for interrupt controller. */ -#define END_OF_INT 0x20 /* code used to re-enable after an interrupt */ - -/* Interrupt vectors defined/reserved by processor. */ -#define DIVIDE_VECTOR 0 /* divide error */ -#define DEBUG_VECTOR 1 /* single step (trace) */ -#define NMI_VECTOR 2 /* non-maskable interrupt */ -#define BREAKPOINT_VECTOR 3 /* software breakpoint */ -#define OVERFLOW_VECTOR 4 /* from INTO */ - -/* Fixed system call vector. */ -#define SYS_VECTOR 32 /* system calls are made with int SYSVEC */ -#define SYS386_VECTOR 33 /* except 386 system calls use this */ -#define LEVEL0_VECTOR 34 /* for execution of a function at level 0 */ - -/* Suitable irq bases for hardware interrupts. Reprogram the 8259(s) from - * the PC BIOS defaults since the BIOS doesn't respect all the processor's - * reserved vectors (0 to 31). - */ -#define BIOS_IRQ0_VEC 0x08 /* base of IRQ0-7 vectors used by BIOS */ -#define BIOS_IRQ8_VEC 0x70 /* base of IRQ8-15 vectors used by BIOS */ -#define IRQ0_VECTOR 0x50 /* nice vectors to relocate IRQ0-7 to */ -#define IRQ8_VECTOR 0x70 /* no need to move IRQ8-15 */ - -/* Hardware interrupt numbers. */ -#define NR_IRQ_VECTORS 16 -#define CLOCK_IRQ 0 -#define KEYBOARD_IRQ 1 -#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ -#define ETHER_IRQ 3 /* default ethernet interrupt vector */ -#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ -#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ -#define XT_WINI_IRQ 5 /* xt winchester */ -#define FLOPPY_IRQ 6 /* floppy disk */ -#define PRINTER_IRQ 7 -#define KBD_AUX_IRQ 12 /* AUX (PS/2 mouse) port in kbd controller */ -#define AT_WINI_0_IRQ 14 /* at winchester controller 0 */ -#define AT_WINI_1_IRQ 15 /* at winchester controller 1 */ - -/* Interrupt number to hardware vector. */ -#define BIOS_VECTOR(irq) \ - (((irq) < 8 ? BIOS_IRQ0_VEC : BIOS_IRQ8_VEC) + ((irq) & 0x07)) -#define VECTOR(irq) \ - (((irq) < 8 ? IRQ0_VECTOR : IRQ8_VECTOR) + ((irq) & 0x07)) - -#endif /* (CHIP == INTEL) */ - -#endif /* _INTERRUPT_H */ Index: trunk/minix/include/ibm/memory.h =================================================================== --- trunk/minix/include/ibm/memory.h (revision 9) +++ (revision ) @@ -1,171 +1,0 @@ -/* Physical memory layout on IBM compatible PCs. Only the major, fixed memory - * areas are detailed here. Known addresses of the BIOS data area are defined - * in . The map upper memory area (UMA) is only roughly defined - * since the UMA sections may vary in size and locus. - * - * Created: March 2005, Jorrit N. Herder - */ - -/* I/O-mapped peripherals. I/O addresses are different from memory addresses - * due to the I/O signal on the ISA bus. Individual I/O ports are defined by - * the drivers that use them or looked up with help of the BIOS. - */ -#define IO_MEMORY_BEGIN 0x0000 -#define IO_MEMORY_END 0xFFFF - - -/* Physical memory layout. Design decisions made for the earliest PCs, caused - * memory to be broken broken into the following four basic pieces: - * - Conventional or base memory: first 640 KB (incl. BIOS data, see below); - * The top of conventional memory is often used by the BIOS to store data. - * - Upper Memory Area (UMA): upper 384 KB of the first megabyte of memory; - * - High Memory Area (HMA): ~ first 64 KB of the second megabyte of memory; - * - Extended Memory: all the memory above first megabyte of memory. - * The high memory area overlaps with the first 64 KB of extended memory, but - * is different from the rest of extended memory because it can be accessed - * when the processor is in real mode. - */ -#define BASE_MEM_BEGIN 0x000000 -#define BASE_MEM_TOP 0x090000 -#define BASE_MEM_END 0x09FFFF - -#define UPPER_MEM_BEGIN 0x0A0000 -#define UPPER_MEM_END 0x0FFFFF - -#define HIGH_MEM_BEGIN 0x100000 -#define HIGH_MEM_END 0x10FFEF - -#define EXTENDED_MEM_BEGIN 0x100000 -#define EXTENDED_MEM_END ((unsigned) -1) - - -/* The logical memory map of the first 1.5 MB is as follows (hexadecimals): - * - * offset [size] (id) = memory usage - * ------------------------------------------------------------------------ - * 000000 [00400] (I) = Real-Mode Interrupt Vector Table (1024 B) - * 000400 [00100] (B) = BIOS Data Area (256 B) - * 000800 [00066] (W) = 80286 Loadall workspace - * 010000 [10000] (c) = Real-Mode Compatibility Segment (64 KB) - * 020000 [70000] (.) = Program-accessible memory (free) - * 090000 [10000] (E) = BIOS Extension - * 0A0000 [10000] (G) = Graphics Mode Video RAM - * 0B0000 [08000] (M) = Monochrome Text Mode Video RAM - * 0B8000 [08000] (C) = Color Text Mode Video RAM - * 0C0000 [08000] (V) = Video ROM BIOS (would be "a" in PS/2) - * 0C8000 [18000] (a) = Adapter ROM + special-purpose RAM (free UMA space) - * 0E0000 [10000] (r) = PS/2 Motherboard ROM BIOS (free UMA in non-PS/2) - * 0F0000 [06000] (R) = Motherboard ROM BIOS - * 0F6000 [08000] (b) = IBM Cassette BASIC ROM ("R" in IBM compatibles) - * 0FD000 [02000] (R) = Motherboard ROM BIOS - * 100000 [.....] (.) = Extended memory, program-accessible (free) - * 100000 [0FFEF] (h) = High Memory Area (HMA) - * - * - * Conventional (Base) Memory: - * - * : [~~~~~16 KB~~~~][~~~~~16 KB~~~~][~~~~~16 KB~~~~][~~~~~16 KB~~~~] - * : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F--- - * 000000: IBW............................................................. - * 010000: cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc - * 020000: ................................................................ - * 030000: ................................................................ - * 040000: ................................................................ - * 050000: ................................................................ - * 060000: ................................................................ - * 070000: ................................................................ - * 080000: ................................................................ - * 090000: EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE - * - * Upper Memory Area (UMA): - * - * : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F--- - * 0A0000: GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG - * 0B0000: MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC - * 0C0000: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa - * 0D0000: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa - * 0E0000: rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr - * 0F0000: RRRRRRRRRRRRRRRRRRRRRRRRbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbRRRRRRRR - * - * Extended Memory: - * - * : 0---1---2---3---4---5---6---7---8---9---A---B---C---D---E---F--- - * 100000: hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh. - * 110000: ................................................................ - * 120000: ................................................................ - * 130000: ................................................................ - * 140000: ................................................................ - * 150000: ................................................................ - * 160000: ................................................................ - * 170000: ................................................................ - * - * Source: The logical memory map was partly taken from the book "Upgrading - * & Repairing PCs Eight Edition", Macmillan Computer Publishing. - */ - - -/* The bottom part of conventional or base memory is occupied by BIOS data. - * The BIOS memory can be distinguished in two parts: - * o The first the first 1024 bytes of addressable memory contains the BIOS - * real-mode interrupt vector table (IVT). The table is used to access BIOS - * hardware services in real-mode by loading a interrupt vector and issuing - * an INT instruction. Some vectors contain BIOS data that can be retrieved - * directly and are useful in protected-mode as well. - * o The BIOS data area is located directly above the interrupt vectors. It - * comprises 256 bytes of memory. These data are used by the device drivers - * to retrieve hardware details, such as I/O ports to be used. - */ -#define BIOS_MEM_BEGIN 0x00000 /* all BIOS memory */ -#define BIOS_MEM_END 0x004FF -#define BIOS_IVT_BEGIN 0x00000 /* BIOS interrupt vectors */ -#define BIOS_IVT_END 0x003FF -#define BIOS_DATA_BEGIN 0x00400 /* BIOS data area */ -#define BIOS_DATA_END 0x004FF - -/* The base memory is followed by 384 KB reserved memory located at the top of - * the first MB of physical memory. This memory is known as the upper memory - * area (UMA). It is used for memory-mapped peripherals, such as video RAM, - * adapter BIOS (adapter ROM and special purpose RAM), and the motherboard - * BIOS (I/O system, Power-On Self Test, bootstrap loader). The upper memory - * can roughly be distinguished in three parts: - * - * o The first 128K of the upper memory area (A0000-BFFFF) is reserved for use - * by memory-mapped video adapters. Hence, it is also called Video RAM. The - * display driver can directly write to this memory and request the hardware - * to show the data on the screen. - */ -#define UMA_VIDEO_RAM_BEGIN 0xA0000 /* video RAM */ -#define UMA_VIDEO_RAM_END 0xBFFFF -#define UMA_GRAPHICS_RAM_BEGIN 0xA0000 /* graphics RAM */ -#define UMA_GRAPHICS_RAM_END 0xAFFFF -#define UMA_MONO_TEXT_BEGIN 0xB0000 /* monochrome text */ -#define UMA_MONO_TEXT_END 0xB7FFF -#define UMA_COLOR_TEXT_BEGIN 0xB8000 /* color text */ -#define UMA_COLOR_TEXT_END 0xBFFFF - -/* o The next 128K (the memory range C0000-DFFFF) is reserved for the adapter - * BIOS that resides in the ROM on some adapter boards. Most VGA-compatible - * video adapters use the first 32 KB of this area for their on-board BIOS. - * The rest can be used by any other adapters. The IDE controller often - * occupies the second 32 KB. - */ -#define UMA_ADAPTER_BIOS_BEGIN 0xC0000 /* adapter BIOS */ -#define UMA_ADAPTER_BIOS_END 0xDFFFF -#define UMA_VIDEO_BIOS_BEGIN 0xC0000 /* video adapter */ -#define UMA_VIDEO_BIOS_END 0xC7FFF -#define UMA_IDE_HD_BIOS_BEGIN 0xC8000 /* IDE hard disk */ -#define UMA_IDE_HD_BIOS_END 0xCBFFF - -/* o The last 128K of the upper memory area (E0000-FFFFF) is reserved for - * motherboard BIOS (Basic I/O System). The POST (Power-On Self Test) and - * bootstrap loader also reside in this space. The memory falls apart in - * two areas: Plug & Play BIOS data and the system BIOS data. - */ -#define UMA_MB_BIOS_BEGIN 0xE0000 /* motherboard BIOS */ -#define UMA_MB_BIOS_END 0xFFFFF -#define UMA_PNP_ESCD_BIOS_BEGIN 0xE0000 /* PnP extended data */ -#define UMA_PNP_ESCD_BIOS_END 0xEFFFF -#define UMA_SYSTEM_BIOS_BEGIN 0xF0000 /* system BIOS */ -#define UMA_SYSTEM_BIOS_END 0xFFFFF - - Index: trunk/minix/include/ibm/partition.h =================================================================== --- trunk/minix/include/ibm/partition.h (revision 9) +++ (revision ) @@ -1,26 +1,0 @@ -/* Description of entry in partition table. */ -#ifndef _PARTITION_H -#define _PARTITION_H - -struct part_entry { - unsigned char bootind; /* boot indicator 0/ACTIVE_FLAG */ - unsigned char start_head; /* head value for first sector */ - unsigned char start_sec; /* sector value + cyl bits for first sector */ - unsigned char start_cyl; /* track value for first sector */ - unsigned char sysind; /* system indicator */ - unsigned char last_head; /* head value for last sector */ - unsigned char last_sec; /* sector value + cyl bits for last sector */ - unsigned char last_cyl; /* track value for last sector */ - unsigned long lowsec; /* logical first sector */ - unsigned long size; /* size of partition in sectors */ -}; - -#define ACTIVE_FLAG 0x80 /* value for active in bootind field (hd0) */ -#define NR_PARTITIONS 4 /* number of entries in partition table */ -#define PART_TABLE_OFF 0x1BE /* offset of partition table in boot sector */ - -/* Partition types. */ -#define NO_PART 0x00 /* unused entry */ -#define MINIX_PART 0x81 /* Minix partition type */ - -#endif /* _PARTITION_H */ Index: trunk/minix/include/ibm/pci.h =================================================================== --- trunk/minix/include/ibm/pci.h (revision 9) +++ (revision ) @@ -1,132 +1,0 @@ -/* -pci.h - -Created: Jan 2000 by Philip Homburg -*/ - -/* Header type 00, normal PCI devices */ -#define PCI_VID 0x00 /* Vendor ID, 16-bit */ -#define PCI_DID 0x02 /* Device ID, 16-bit */ -#define PCI_CR 0x04 /* Command Register, 16-bit */ -#define PCI_CR_MAST_EN 0x0004 /* Enable Busmaster Access */ -#define PCI_CR_IO_EN 0x0001 /* Enable I/O Cycles */ -#define PCI_SR 0x06 /* PCI status, 16-bit */ -#define PSR_SSE 0x4000 /* Signaled System Error */ -#define PSR_RMAS 0x2000 /* Received Master Abort Status */ -#define PSR_RTAS 0x1000 /* Received Target Abort Status */ -#define PSR_CAPPTR 0x0010 /* Capabilities list */ -#define PCI_REV 0x08 /* Revision ID */ -#define PCI_PIFR 0x09 /* Prog. Interface Register */ -#define PCI_SCR 0x0A /* Sub-Class Register */ -#define PCI_BCR 0x0B /* Base-Class Register */ -#define PCI_CLS 0x0C /* Cache Line Size */ -#define PCI_LT 0x0D /* Latency Timer */ -#define PCI_HEADT 0x0E /* Header type, 8-bit */ -#define PHT_MASK 0x7F /* Header type mask */ -#define PHT_NORMAL 0x00 -#define PHT_BRIDGE 0x01 -#define PHT_CARDBUS 0x02 -#define PHT_MULTIFUNC 0x80 /* Multiple functions */ -#define PCI_BIST 0x0F /* Built-in Self Test */ -#define PCI_BAR 0x10 /* Base Address Register */ -#define PCI_BAR_IO 0x00000001 /* Reg. refers to I/O space */ -#define PCI_BAR_TYPE 0x00000006 /* Memory BAR type */ -#define PCI_BAR_PREFETCH 0x00000008 /* Memory is prefetchable */ -#define PCI_BAR_2 0x14 /* Base Address Register */ -#define PCI_BAR_3 0x18 /* Base Address Register */ -#define PCI_BAR_4 0x1C /* Base Address Register */ -#define PCI_BAR_5 0x20 /* Base Address Register */ -#define PCI_BAR_6 0x24 /* Base Address Register */ -#define PCI_CBCISPTR 0x28 /* Cardbus CIS Pointer */ -#define PCI_SUBVID 0x2C /* Subsystem Vendor ID */ -#define PCI_SUBDID 0x2E /* Subsystem Device ID */ -#define PCI_EXPROM 0x30 /* Expansion ROM Base Address */ -#define PCI_CAPPTR 0x34 /* Capabilities Pointer */ -#define PCI_CP_MASK 0xfc /* Lower 2 bits should be ignored */ -#define PCI_ILR 0x3C /* Interrupt Line Register */ -#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */ -#define PCI_IPR 0x3D /* Interrupt Pin Register */ -#define PCI_MINGNT 0x3E /* Min Grant */ -#define PCI_MAXLAT 0x3F /* Max Latency */ - -/* Header type 01, PCI-to-PCI bridge devices */ -/* The following registers are in common with type 00: - * PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR, - * PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_BAR2, PCI_CAPPTR, - * PCI_ILR, PCI_IPR. - */ -#define PPB_PRIMBN 0x18 /* Primary Bus Number */ -#define PPB_SECBN 0x19 /* Secondary Bus Number */ -#define PPB_SUBORDBN 0x1A /* Subordinate Bus Number */ -#define PPB_SECBLT 0x1B /* Secondary Bus Latency Timer */ -#define PPB_IOBASE 0x1C /* I/O Base */ -#define PPB_IOB_MASK 0xf0 -#define PPB_IOLIMIT 0x1D /* I/O Limit */ -#define PPB_IOL_MASK 0xf0 -#define PPB_SSTS 0x1E /* Secondary Status Register */ -#define PPB_MEMBASE 0x20 /* Memory Base */ -#define PPB_MEMB_MASK 0xfff0 -#define PPB_MEMLIMIT 0x22 /* Memory Limit */ -#define PPB_MEML_MASK 0xfff0 -#define PPB_PFMEMBASE 0x24 /* Prefetchable Memory Base */ -#define PPB_PFMEMB_MASK 0xfff0 -#define PPB_PFMEMLIMIT 0x26 /* Prefetchable Memory Limit */ -#define PPB_PFMEML_MASK 0xfff0 -#define PPB_PFMBU32 0x28 /* Prefetchable Memory Base Upper 32 */ -#define PPB_PFMLU32 0x2C /* Prefetchable Memory Limit Upper 32 */ -#define PPB_IOBASEU16 0x30 /* I/O Base Upper 16 */ -#define PPB_IOLIMITU16 0x32 /* I/O Limit Upper 16 */ -#define PPB_EXPROM 0x38 /* Expansion ROM Base Address */ -#define PPB_BRIDGECTRL 0x3E /* Bridge Control */ -#define PPB_BC_CRST 0x40 /* Assert reset line */ - -/* Header type 02, Cardbus bridge devices */ -/* The following registers are in common with type 00: - * PCI_VID, PCI_DID, PCI_CR, PCI_SR, PCI_REV, PCI_PIFR, PCI_SCR, PCI_BCR, - * PCI_CLS, PCI_LT, PCI_HEADT, PCI_BIST, PCI_BAR, PCI_ILR, PCI_IPR. - */ -/* The following registers are in common with type 01: - * PPB_PRIMBN, PPB_SECBN, PPB_SUBORDBN, PPB_SECBLT. - */ -#define CBB_CAPPTR 0x14 /* Capability Pointer */ -#define CBB_SSTS 0x16 /* Secondary Status Register */ -#define CBB_MEMBASE_0 0x1C /* Memory Base 0 */ -#define CBB_MEMLIMIT_0 0x20 /* Memory Limit 0 */ -#define CBB_MEML_MASK 0xfffff000 -#define CBB_MEMBASE_1 0x24 /* Memory Base 1 */ -#define CBB_MEMLIMIT_1 0x28 /* Memory Limit 1 */ -#define CBB_IOBASE_0 0x2C /* I/O Base 0 */ -#define CBB_IOLIMIT_0 0x30 /* I/O Limit 0 */ -#define CBB_IOL_MASK 0xfffffffc -#define CBB_IOBASE_1 0x34 /* I/O Base 1 */ -#define CBB_IOLIMIT_1 0x38 /* I/O Limit 1 */ -#define CBB_BRIDGECTRL 0x3E /* Bridge Control */ -#define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */ -#define CBB_BC_CRST 0x40 /* Assert reset line */ - -#define CAP_TYPE 0x00 /* Type field in capability */ -#define CAP_NEXT 0x01 /* Next field in capability */ - -#define PCI_BCR_MASS_STORAGE 0x01 /* Mass Storage class */ -#define PCI_MS_IDE 0x01 /* IDE storage class */ -#define PCI_IDE_PRI_NATIVE 0x01 /* Primary channel is - * in native mode. - */ -#define PCI_IDE_SEC_NATIVE 0x04 /* Secondary channel is - * in native mode. - */ - -/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */ -#define PCI_T3_VGA_OLD 0x000100 /* OLD VGA class code */ -#define PCI_T3_RAID 0x010400 /* RAID controller */ -#define PCI_T3_VGA 0x030000 /* VGA-compatible video card */ -#define PCI_T3_ISA 0x060100 /* ISA bridge */ -#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */ -#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */ -#define PCI_T3_CARDBUS 0x060700 /* Bardbus Bridge */ - -#define NO_VID 0xffff /* No PCI card present */ - -/* - * $PchId: pci.h,v 1.4 2001/12/06 20:21:22 philip Exp $ - */ Index: trunk/minix/include/ibm/portio.h =================================================================== --- trunk/minix/include/ibm/portio.h (revision 9) +++ (revision ) @@ -1,29 +1,0 @@ -/* -ibm/portio.h - -Created: Jan 15, 1992 by Philip Homburg -*/ - -#ifndef _PORTIO_H_ -#define _PORTIO_H_ - -#ifndef _TYPES_H -#include -#endif - -unsigned inb(U16_t _port); -unsigned inw(U16_t _port); -unsigned inl(U32_t _port); -void outb(U16_t _port, U8_t _value); -void outw(U16_t _port, U16_t _value); -void outl(U16_t _port, U32_t _value); -void insb(U16_t _port, void *_buf, size_t _count); -void insw(U16_t _port, void *_buf, size_t _count); -void insl(U16_t _port, void *_buf, size_t _count); -void outsb(U16_t _port, void *_buf, size_t _count); -void outsw(U16_t _port, void *_buf, size_t _count); -void outsl(U16_t _port, void *_buf, size_t _count); -void intr_disable(void); -void intr_enable(void); - -#endif /* _PORTIO_H_ */ Index: trunk/minix/include/ibm/ports.h =================================================================== --- trunk/minix/include/ibm/ports.h (revision 9) +++ (revision ) @@ -1,17 +1,0 @@ -/* Addresses and magic numbers for miscellaneous ports. */ - -#ifndef _PORTS_H -#define _PORTS_H - -#if (CHIP == INTEL) - -/* Miscellaneous ports. */ -#define PCR 0x65 /* Planar Control Register */ -#define PORT_B 0x61 /* I/O port for 8255 port B (kbd, beeper...) */ -#define TIMER0 0x40 /* I/O port for timer channel 0 */ -#define TIMER2 0x42 /* I/O port for timer channel 2 */ -#define TIMER_MODE 0x43 /* I/O port for timer mode control */ - -#endif /* (CHIP == INTEL) */ - -#endif /* _PORTS_H */